HLDVT Call for Participation
IEEE International High Level Design Validation and Test Workshop
The Claremont Resort & Spa, Oakland, California
Nov. 15-16, 1996
CALL FOR PARTICIPATION
Sponsored by the IEEE Computer Society Test Technology Technical Committee,
and the IEEE Computer Society Design Automation Technical Committee.
The First IEEE International High Level Design Validation and Test
Workshop aims to stimulate research in test and validation
methodologies for ICs and systems specified using high level
descriptions, where high level refers to register-transfer,
behavioral, and system level. The goal of the workshop is to provide
an informal forum, bringing together designers and test and
verification researchers working in validating, debugging,
synthesizing, and testing designs specified using high level
descriptions, in an effort to address high level design, validation,
and test issues concurrently. Major topics include, but are not
limited to, the following:
| High Level Design Validation | High Level DFT/Synthesis for Test |
| High Level Design Error Modeling | High Level ATPG/Fault Simulation |
| High Level Testbench Generation | Hardware/Software Co-Testing |
| Design Error Debug/Diagnosis | Testing Core Based Designs |
| Hardware/Software Co-Validation | Hybrid Test & Validation Techniques |
The Program Committee invites authors to submit an extended summary
comprising up to 1000 words describing original, unpublished recent
work. Clearly describe the nature of the work, explain its
significance, highlight novel features, and describe its current
status. On the title page, please indicate: title, name, and
affiliations of all authors, and suggested topics. Also identify a
contact author and include a complete mailing address, phone number, fax
number, and E-mail address. Panel proposals are also invited. Submit
seven copies of proposal by mail or a Postscript version via E-mail.
Submissions are due no later than August 7, 1996.
| Submit all paper proposals to: |
For general information, contact: |
| Sujit Dey, Program Chair | Prab Varma, General Chair |
| NEC USA | CrossCheck Technology |
| 4 Independence Way | 2833 Junction Ave., #100 |
| Princeton, NJ 08540 | San Jose, CA 95134 |
| T: 609-951-2973, F: 609-951-2499 | T: 408-432-9200, F: 408-432-0907 |
| E-mail: dey@ccrl.nj.nec.com | E-mail: prab@crosscheck.com |
| Organizing Committee: |
| General Chair: | P. Varma, CrossCheck |
| Vice-General Chair: | P. Marwedel, Univ. of Dortmund |
| Program Chair: | S. Dey, NEC USA |
| Finance: | A. Orailoglu, UC San Diego |
| Publicity: | M. Fujita, Fujitsu Labs of America |
| Local Arrangements: | V. Nagasamy, LSI Logic |
| European Liasion: | B. Courtois, TIMA |
| Asian Liasion: | H. Fujiwara, NAIST |
| Program Committee: |
| M. Abadir | Motorola |
| J. Abraham | Univ of Texas at Austin |
| B. Bennetts | Logic Vision |
| R. Bergamaschi | IBM |
| S. Bhatia | CrossCheck |
| F. Brglez | NCSU |
| R. Bryant | CMU |
| K-T. Cheng | UCSB |
| D.D. Gajski | UCI |
| J. Jess | Eindhoven Univ |
| A. Kuehlman | IBM |
| D. Ku | Escalade |
| W. Kunz | Univ of Potsdam |
| J. Lu | National Semiconductors |
| M. Marzoukui | TIMA |
| E.J. McCluskey | Stanford Univ |
| B. Nadeau-Dostie | LVS |
| V. Nagasamy | LSI Logic |
| C. Papachristou | CWRU |
| C. Pixley | Motorola |
| I. Pomeranz | U. Iowa |
| M. Potkonjak | UCLA |
| P. Prinetto | Poli. di Torino |
| J. Rajski | Mentor Graphics |
| W. Rosenstiel | Tuebingen Univ |
| B. Rouzeyre | LIRMM |
| R. Roy | NEC USA |
| R. Vemuri | Univ of Cincinnati |
| P. Verhofstadt | SRC |
| H. Yasuura | Kyushu Univ |
| Y. Zorian | Lucent Bell Labs |
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