
The Third International High Level Design Validation and Test Workshop is sponsored by the IEEE Computer Society Test Technology Technical Committee and the IEEE Computer Society Design Automation Technical Committee.
The Third IEEE International High Level Design Validation and Test Workshop aims to stimulate research in test and validation methodologies for ICs and systems specified using high level descriptions, where high level refers to register-transfer, behavioral, and system level specifications. The goal of the workshop is to provide an informal forum, bringing together designers and test and verification researchers working in validating, debugging, and testing designs, in an effort to address high level design validation and test issues concurrently. Major topics include, but are not limited to, the following:
| High Level Design Validation | Hardware/Software Co-Validation |
| High Level Design Error Modeling | High Level DFT/Synthesis for Test |
| High Level Test Bench Generation | High Level ATPG/Fault Simulation |
| Testing Core Based Designs | Validation of Microprocessors |
| Hardware/Software Co-Testing | Design Error Debug & Diagnosis |
The Program Committee invites authors to submit an extended summary comprising 1000 words describing original, unpublished recent work. Clearly describe the nature of the work, explain its significance, highlight novel features, and describe its current status. On the title page, please indicate: title, name and affiliations of all authors, and suggested topics. Also identify a contact author and include a complete mailing address, phone number, fax number and E-mail address. Panel proposals are also invited. Submit seven copies of proposals by mail or a Postscript version via E-mail. Submissions are due no later than July 15, 1998.
| Submit all paper proposals to: | For general information, contact: |
| Alex Orailoglu, Program Chair | Sujit Dey, General Chair |
| Dept. of Computer Science & Engr. | Dept. of Electrical & Computer Engr. |
| University of California, San Diego | University of California, San Diego |
| La Jolla, CA 92093-0114 | La Jolla, CA 92093-0407 |
| T: 619-534-0914, F: 619-534-7029 | T: 619-534-0750, F: 619-534-0415 |
| E-mail: alex@cs.ucsd.edu | E-mail: dey@ece.ucsd.edu |
Authors will be notified of the disposition of their papers by September 4, 1998. The submission of a proposal will be considered evidence that upon acceptance the author(s) will present the paper at the workshop. Authors of accepted papers may submit a full version of their paper by October 5, 1998 for inclusion in an informal digest of papers, which will be distributed only to attendees of the workshop.
| General Chair | S. Dey, UC San Diego |
| Vice-General Chair | P. Marwedel, U. Dortmund |
| Program Chair | A. Orailoglu, UC San Diego |
| Finance Chair | P. Varma, Duet Technologies Inc. |
| Publicity Chair | R. Raina, Motorola Inc. |
| Panels Chair | M. Fujita, Fujitsu Labs |
| Proceedings Chair | V. Nagasamy, VSIS, Inc. |
| Local Arrangements Chair | R. Gupta, UC Irvine |
| European Liaison | B. Courtois, TIMA |
| Asian Liaison | H. Yasuura, Kyushu University |
| Industry Liaison | J-P. Masbou, Intel Corp. |
| M. Abadir | Motorola |
| J. Abraham | Univ. of Texas |
| T. Ambler | Univ. of Texas |
| A. Basu | Indian Institute of Tech., KGP |
| R. Bergamaschi | IBM |
| S. Bhatia | Duet Technologies |
| F. Brglez | NCSU |
| F. Catthoor | IMEC |
| K-T. Cheng | UCSB |
| H. Date | ISIT/KYUSHU |
| D. Dill | Stanford Univ. |
| J.P. Hayes | Univ. of Michigan |
| J. Jess | Eindhoven Univ |
| R. Karri | Lucent Bell Labs |
| D. Ku | Escalade |
| M. Lee | Avant! |
| S. Leef | Mentor Graphics |
| L. Lavagno | Politecnico di Torino |
| J. Lu | National Semiconductor |
| E.J. McCluskey | Stanford Univ. |
| C. Papachristou | CWRU |
| I. Pomeranz | Univ. of Iowa |
| M. Potkonjak | UCLA |
| P. Prinetto | Politecnico di Torino |
| J. Rajski | Mentor Graphics |
| W. Rosenstiel | Tuebingen Univ |
| B. Rouzeyre | LIRMM |
| R. Roy | Intel |
| A. Takahara | NTT |
| Y. Zorian | LogicVision |