IEEE International High Level Design Validation and Test Workshop The Claremont Resort & Spa, Oakland, California Nov. 14-15, 1997 Call For Participation The Second IEEE International High Level Design Validation and Test Workshop aims to stimulate research in test and validation methodolo- gies for ICs and systems specified using high level descriptions, where high level refers to register-transfer, behavioral, and system level specifications. The goal of the workshop is to provide an infor- mal forum, bringing together designers and test and verification researchers working in validating, debugging, and testing designs, in an effort to address high level design validation and test issues con- currently. Major topics include, but are not limited to, the follow- ing: High Level Design Validation Hardware/Software Co-Validation High Level Design Error Modeling High Level DFT/Synthesis for Test High Level Test Bench Generation High Level ATPG/Fault Simulation Testing Core Based Designs Validation of Microprocessors Hardware/Software Co-Testing Design Error Debug & Diagnosis The Program Committee invites authors to submit an extended summary comprising 1000 words describing original, unpublished recent work. Clearly describe the nature of the work, explain its significance, highlight novel features, and describe its current status. On the title page, please indicate: title, name and affiliations of all authors, and suggested topics. Also identify a contact author and include a complete mailing address, phone number, fax number and E- mail address. Panel proposals are also invited. Submit seven copies of proposals by mail or a Postscript version via E-mail. Submissions are due no later than August 1, 1997. Submit all paper proposals to: For general information, contact: Sujit Dey, Program Chair Prab Varma, General Chair NEC USA Duet Technologies Inc. 4 Independence Way 2833 Junction Ave., #100 Princeton, NJ 08540 San Jose, CA 95134 T: 609-951-2973, F: 609-951-2499 T: 408-432-9200, F: 408-432-0907 E-mail: dey@ccrl.nj.nec.com E-mail: prab@duettech.com Authors will be notified of the disposition of their papers by September 15, 1997. The submission of a proposal will be considered evidence that upon acceptance the author(s) will present the paper at the workshop. Authors of accepted papers may submit a full version of their paper by October 15, 1997 for inclusion in an informal digest of papers, which will be distributed only to attendees of the workshop. The Second International High Level Design Validation and Test Workshop is sponsored by the IEEE Computer Society Test Technology Technical Committee and the IEEE Computer Society Design Automation Technical Committee. HLDVT'97 Steering Committee General Chair P. Varma Duet Technologies Inc. Vice-General Chair P. Marwedel U. Dortmund Program Chair S.Dey NEC USA Finance Chair A. Orailoglu UC San Diego Publicity Chair M. Fujita Fujitsu Labs Proceedings Chair R.Raina Motorola Inc. European Liaison B.Courtois TIMA Asian Liaison H.Yasuura Kyushu University Member At Large V.Nagaswamy VSI Program Committee (to include) M.Abadir - Motorola J.Abraham - U. Texas B.Bennetts - LogicVision R.Bergamaschi - IBM S.Bhatia - Duet Technologies F.Brglez - NCSU K.T.Cheng - UCSB R.Gupta - UCI A.Jerraya - TIMA J.Jess - U. Eindhoven R.Gupta - UCI D.Ku - Escalade L.Lavagno-P. di Torino/CBL J.Lu - Nat. Semiconductors J.P. Masbou - Intel E.J.McCluskey-Stanford U C.Papachristou - CWRU C.Pixley - Motorola I.Pomeranz - U. Iowa M.Potkonjak - UCLA J.Rajski - Mentor Graphics W.Rosenstiel -Tuebingen U B.Rouzeyre - LIRMM R.Roy - NEC USA Y.Zorian - LogicVision