Recent paper by Larry Carter

• O. Beaumont, L. Carter, J. Ferrante, A. Legrand, L. Marchal, and Y. Robert, "Centralized versus Distributed Schedulers for Multiple Bag-of-task Applications", IEEE International Parallel and Distributed Processing Symposium (IPDPS'06).

• B. Kreaseck, L. Carter, H. Casanova, J. Ferrante, and S. Nandy, "Interference-Aware Scheduling", International Journal of High Performance Computing Applications, Vol 20, No 1, (2006).

• X. Gao, A. Snavely, and L. Carter, "Path Grammar Guided Trace Compression and Trace Approximation", IEEE International Symposium on High-Performance Distributed Computing (HPDC'06).

• S. Nandy, L. Carter, and J. Ferrante, "GUARD: Gossip Used for Autonomous Resource Detection", IEEE International Parallel and Distributed Processing Symposium (IPDPS'05).

• S. Nandy, L. Carter, and J. Ferrante, "A-FAST: Autonomous Flow Approach to Scheduling Tasks", International Conference in High-Performance Computing (HiPC'04), published in Springer LNCS 3296, pp 363-374 (2004).

• C. Banino, O. Beaumont, L. Carter, J. Ferrante, A. Legrand, and Y. Robert, "Scheduling Strategies for Master-Slave Tasking on Heterogeneous Processor Platforms", IEEE Transactions on Parallel and Distributed Systems, Volume 15, Number 4, pages 319-330. (April, 2004)

• B. Kreaseck, L. Carter, H. Casanova, and J. Ferrante, "On the Interference of Communication on Computation in Java", Third International Workshop on Performance Modeling, Evaluation, and Optimization of Parallel and Distributed Systems (PMEO'04).

• M. Mills Strout, L. Carter, J. Ferrante, and B. Kreaseck, "Sparse Tiling for Stationary Iterative Methods", International Journal of High-Performance Computing Applications, Volume 18, Number 1, pages 95-113 (2004).

• M. Mills Strout, L. Carter, and J. Ferrante, "Compile-time Composition of Run-time Data and Iteration Reorderings", Conference on Programming Language Design and Implementation (PLDI'03).

• B. Kreaseck, L. Carter, H. Casanova, and J. Ferrante, "Autonomous Protocols for Bandwidth-Centric Scheduling of Independent Task Applications", IEEE International Parallel and Distributed Processing Symposium (IPDPS'03).

• L. Carter, J. Ferrante, and C. Thomborson, "Folklore Confirmed: Reducible Flow Graphs are Exponentially Larger", Conference on Principles of Programming Languages (POPL'03).

• K. Hogstedt, L. Carter ,and J. Ferrante, "On the Parallel Execution Time of Tiled Loops", IEEE Transactions on Parallel and Distributed Systems, Volume 14, Number 3, pages 307-321 (2003).

• M. Mills Strout, L. Carter, J. Ferrante, J. Freeman, and B. Kreaseck, "Combining Performance Aspects of Irregular Gauss-Seidel via Sparse Tiling", Languages and Compilers for Parallel Computing (LCPC) workshop, 2002.

• O. Beaumont, L. Carter, J. Ferrante, A. Legrand, and Y. Robert, "Bandwidth-centric allocation of independent tasks on heterogeneous platforms", International Parallel and Distributed Processing Symposium (IPDPS'2002).

• M. Mills Strout, L. Carter, and J. Ferrante, "Rescheduling for Locality in Sparse Matrix Computations", International Conference on Scientific Computation, May, 2001, published in Springer LNCS 2073. Here also are a pdf version of the paper and slides for Michelle Strout's talk.

• N.Mitchell, L. Carter, and J.Ferrante, ``A Modal Model of Memory'', International Conference on Scientific Computation, special session on Architecture-Specific Performance Tuning, May 2001, published in Springer LNCS 2073.

• Kang Su Gatlin and Larry Carter, ``Faster FFTs via Architecture Cognizance'', PACT2000, October 2000.

• Lori Carter, Beth Simon, Brad Calder, Larry Carter, Jeanne Ferrante, "Path Analysis and Renaming for Predicated Instruction Scheduling", International Journal of Parallel Programming, Volum3 28, Number 6 (2000).

• Allan Snavely and Larry Carter, ``Symbiotic Jobscheduling on the Tera MTA'', Workshop on Multi-Threaded Execution, Architecture and Compilation (MTEAC'00), January, 2000. And here's an (incomplete) html version.

• Larry Carter and Jeanne Ferrante, editors, "Languages and Compilers for Parallel Computing" (Proceedings from the 1999 LCPC Workshop), Springer Lecture Notes in Computer Science number 1863.

• Kang Su Gatlin and Larry Carter, ``Architecture-Cognizant Divide and Conquer Algorithms'', Supercomputing '99, November 1999. Here's a pdf version.

• Nick Mitchell, Larry Carter, Jeanne Ferrante, and Dean Tullsen, ``ILP versus TLP on SMT'', Supercomputing '99, November 1999. Here's a pdf version.

• V. Getov, Y. Wei, L. Carter, and K Gatlin, ``Performance Optimisations of the NPB FT Kernel by Special-Purpose Unroller'', 7th Euromicro Workshop on Parallel and Distributed Processing (PDP'99), February, 1999.

• Nick Mitchell, Larry Carter, and Jeanne Ferrante, ``Localizing Non-affine Array References'', PACT '99, October 1999. Here's a pdf version.

• Lori Carter, Beth Simon, Brad Calder, Larry Carter, and Jeanne Ferrante, ``Predicated Static Single Assignment'', Parallel Architectures and Compilation Techniques (PACT99), October 1999.

• K. Högstedt, L. Carter, and J. Ferrante, ``Selecting Tile Shape for Minimal Execution Time,'' ACM Symposium on Parallel Algorithms and Architectures (SPAA'99),, June, 1999.

• Tung Nguyen, Michelle Mills Strout, Larry Carter, and Jeanne Ferrante, ``Asynchronous Dynamic Load Balancing of Tiles'', SIAM99 Conference on Parallel Processing, March 1999. Here's a preliminary version with a few more details on the algorithm.

• Larry Carter, John Feo, and Allan Snavely, ``Performance and Programming Experience on the Tera MTA'', SIAM Conference on Parallel Processing, March 1999. Here's a pdf version.

• Allan Snavely, Nick Mitchell, Larry Carter, Jeanne Ferrante, and Dean Tullsen, ``Explorations in Symbiosis on two Multithreaded Architectures'', MTEAC99, January 1999.

• K.S. Gatlin and Larry Carter, ``Memory Hierarchy Considerations for Fast Transpose and Bit-Reversals'', HPCA99, January 1999.

• L. Carter and K.S. Gatlin, ``Towards an Optimal Bit-Reversal Permutation Program'', FOCS, November 1998. Here's a pdf version.

• A. Snavely and L. Carter, with J. Boisseau, A. Majumdar, K.S. Gatlin, N. Mitchell, J. Feo, and B. Koblenz, ``Multi-processor Performance on the Tera MTA'', Supercomputing '98, November 1998.

• M. Strout, L. Carter, J. Ferrante, and B. Simon, ``Schedule-Independent Storage Mapping for Loops'', ASPLOS, October, 1998.

• Boisseau, J., L. Carter, A. Snavely, D. Callahan, J. Feo. S. Kahan, and Z. Wu, ``CRAY T90 vs. Tera MTA: The Old Champ Faces a New Challenger'', Cray User's Group Conference, June 1998.

• Boisseau, J., L. Carter, K.S. Gatlin, A. Majumdar and A. Snavely, ``NAS Benchmarks on the Tera MTA,'' Workshop on Multi-Threaded Execution, Architecture and Compilation (M-TEAC 98), February 1998.

• Mitchell, N., K. Högstedt, L. Carter, and J. Ferrante, ``Quantifying the Multi-Level Nature of Tiling Interactions,'' International Journal of Parallel Programming, Vol 26, No 6 pp 641-670 (1998). (Special issue from 1997 LCPC workshop.)

• Mitchell, N., L. Carter, J. Ferrante, and K. Högstedt, ``Quantifying the Multi-Level Nature of Tiling Interactions,'' 10th International Workshop on Languages and Compilers for Parallel Computing,, August, 1997. Proceedings appeared as Springer, Lecture Notes in Computer Science, vol. 1366, pp 1--15 (1998).

• Mitchell, N., L. Carter, and J. Ferrante, ``A Compiler Perspective on Architectural Evolutions,'' Workshop on Interactions between Compilers and Computer Architectures, Feb 1997.

• Högstedt, K., L. Carter, and J. Ferrante, ``Determining the Idle Time of a Tiling,'' Symposium on Principle of Programming Languages (POPL), Jan 1997. (See also UCSD Tech Report CS96-489, Jan 1997.)

• Carter, L., J. Ferrante, S. Flynn Hummel, B. Alpern, and K.S. Gatlin, ``Hierarchical Tiling: A Methodology for High Performance,'' UCSD Tech Report CS96-508, Nov 1996.

• Agarwal, R. C., B. Alpern, L. Carter, F. G. Gustavson, D. Klepacki, R. Lawrence, and M. Zubair, ``High Performance Parallel Implementations of the NAS Kernel Benchmarks on the IBM SP2,'' IBM Systems Journal, Vol 34, No. 2, pp 263--272 (1995)

• Alpern, B., L. Carter, and K. S. Gatlin, ``Microparallelism and High-Performance Protein Matching,'' SuperComputing '95.

• L. Carter, ``RISC from a Performance Programmer's Perspective,'' Invited talk, IBM "RISC in 1995" Symposium, November 1995.

• Alpern, B., L. Carter, and J. Ferrante, ``Space-Limited Procedures: A Methodology for Portable High-Performance,'' International Working Conference on Massively Parallel Programming Models, 1995.

• L. Carter, J. Ferrante and S. Flynn Hummel, ``Hierarchical Tiling for Improved Superscalar Performance,'' International Parallel Processing Symposium April, 1995.

• Alpern, B. and L. Carter, ``The Myth of Scalable High Performance,'' SIAM Conference on Parallel Processing for Scientific Computing, February 1995.

• Alpern, B. and Carter L., ``Is Scalability Relevant: A Look at Sparse Matrix-Vector Product,'' SIAM Conference on Parallel Processing for Scientific Computing, February 1995.

• Alpern, B. and Carter L., ``Message Compression for High Performance,'' SIAM Conference on Parallel Processing for Scientific Computing, February 1995.

• L. Carter, J. Ferrante and S. Flynn Hummel, ``Efficient Multiprocessor Parallelism via Hierarchical Tiling,'' SIAM Conference on Parallel Processing for Scientific Computing, February 1995.

• Alpern, B. and L. Carter, ``Performance Programming: A Science Waiting to Happen,'' Developing a Computer Science Agenda for High-Performance Computing, Viskin, U. ed., ACM Press, 1994.

• Alpern, B., L. Carter, E. Feig, and T. Selker, ``The Uniform Memory Hierarchy Model of Computation,'' Algorithmica, Volume 12, Number 2-3, August-September 1994.

• Alpern B. and L. Carter, ``Towards a Model for Portable Parallel Performance: Exposing the Memory Hierarchy,'' Portability and Performance for Parallel Processing, Hey T. and J. Ferrante ed., John Wiley and Sons, 1994.

• C. Thomborson, B. Alpern, and L. Carter, ``Rectilinear Steiner Tree Minimization on a Workstation,'' Computational Support for Discrete Mathematics, Dean, N. and G. Shannon ed., DIMACS Series in Discrete Mathematics and Theoretical Computer Science, 1994.

• Alpern, B., L. Carter, and J. Ferrante, ``Modeling Parallel Computers as Memory Hierarchies,'' Programming Models for Massively Parallel Computers, Giloi, W. K., S. Jahnichen, and B. D. Shriver ed., IEEE Press, 1993.

• Almasi, G., B. Alpern, L. Berman, L. Carter, and D. Hale, ``A Case-Study in Performance Programming: Seismic Migration,'' Symposium on High Performance Computing, September 1991.