Eric Tune

I also have a personal home page, here.

Research Page

My name is Eric Tune.

I was a PhD student at University of California, San Diego . My PhD advisors were Dean Tullsen and Brad Calder. My research was focused on computer architecture.

My research interests include multithreading and critical-path prediction.

Critical path prediction seeks to identify which instructions are limiting performance, and which are not, and to steer instructions to processor resources according to their criticality. Critical path predictions can be made in hardware, at runtime, with the addition of a small table and some control logic. The predictor can be used in many ways. It can be used to mitigate the performance impact of a reduced-power processor design, with multi-speed functional units. It can be used to steer instructions in a clustered microarchitecture, to hide the effect of wire delays. It can also be used to make value prediction more effective, or to control the placement of data in the cache hierarchy.

Simultaneous multithreading (SMT) is the best way to add additional thread-context to a several additional contexts to a single-threaded microprocessor design. In order to maintain good utilization of processor resources in the face of a growing gap between processor speed and main-memory latency, a processor core needs to support a larger number of threads. My research has investigates several techniques which allow increasing the number of thread contexts on an SMT processor without significantly diminishing single- or few-thread performance. These techniques are Balanced Multithreading, and register caching.

I ported the SMTSIM simulator to C++, and reorganized the code to use generic programming and object-oriented programming principles, while maintaining good simulation speed. I was inspired by the excellent ASIM simulator. If you are interested in this code, send me e-mail.

Papers

Critical-Path Prediction

Eric Tune "Critical-Path Aware Processor Architectures" (pdf) (compressed ps) Ph.D. Thesis (Also UCSD CSE Tech Report: #CS2004-0808)

Eric Tune, Dean Tullsen, Brad Calder "Quantifying Instruction Criticality" Eleventh Int'l Conf. on Parallel Architectures and Compilation Techniques, Charlottesville, VA, Sep., 2002

John Seng, Eric Tune, Dean Tullsen, George Cai "Reducing Processor Power with Critical Path Prediction" 34th International Symposium on Microarchitecture, Austin, Texas, Dec., 2001

Eric Tune, Dongning Liang, Brad Calder, Dean Tullsen "Dynamic Prediction of the Critical Performance Path" Seventh International Symposium on High-Performance Computer Architecture, Monterrey, Mexico, Jan., 2001

Scalability of Multithreading

Eric Tune, Rakesh Kumar, Dean Tullsen, Brad Calder "Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading Hierarchy" 37th International Symposium on Microarchitecture, Portland, Oregon, Dec., 2004 (Slides)

Eric Borch, Eric Tune, Bobbie Manne, Joel Emer "Loose Loops Sink Chips" Eighth International Symposium on High-Performance Computer Architecture, Cambridge, Mass, Feb., 2002