Gilles POKAM

E-mail:	gpokam@cs.ucsd.edu
Postal:	Gilles POKAM University of California, San Diego Department of Computer Science and Engineering 9500 Gilman Dr, La Jolla, CA 92093-0404
Where:	High-Performance Processor Architecture and Compilation Lab EBU 3B Room 3226
Work Phone:	1-858-534-8642

About me

I'm postdoc researcher at UCSD, working for Prof. Brad Calder. Previously, I used to be a member of the CAPS team, at IRISA, working for Prof. F. Bodin. I obtained a PhD degree in Computer Science in July 2004 with the CAPS group. From March 2000 to January 2001, I worked as research engineer in the CAPS group, conducting advanced developments in compiler with emphasis on general purpose compiler environment for application specific processors. In January 2000 I obtained a MS degree in Computer Science and Engineering from the Technical University of Berlin (Germany).

Curriculum Vitae

pdf , html

Research interests

My main research interests broadly span the interactions between compiler and computer architecture. Currently, I'm interested in the following research topics:

Computer architecture
Compiler optimizations
Program Analysis and Optimization
Hardware/Software support for debugging
Low-Power and Complexity-effective architectures
Parallel programming models and architecture

Publications

Journal Articles

O. Rochecouste, G. Pokam and A. Seznec. A Case for a Complexity-Effective, Width-Partitioned Microarchitecture. ACM Transactions on Architecture and Code Optimization (ACM-TACO), Vol 3, No. 3, September 2006, Pages 295-326. [pdf].

S. Narayanasamy, G. Pokam and B. Calder. BugNet: Recording Application Level Execution for Deterministic Replay Debugging. IEEE Micro Special Issue: Top Picks from Computer Architecture Conferences (Micro's Top Picks), Jan/Feb 2006. [pdf].

G. Pokam, S. Bihan, J. Simonnet, and F. Bodin. SWARP: A Retargetable Preprocessor for Multimedia Instructions. Concurrency and Computation: Practice and Experience (CCPE), Volume 16, Issue 2-3, p 303 - 318, February - March 2004. [gziped].

Conference/Workshop Papers

W. Chuang, S. Narayanasamy, G. Venkatesh, J. Sampson, M. Van Biesbrouck, G. Pokam, O. Colavin and B. Calder. Unbounded Page-Based Transactional Memory. In Proceedings of the Twelfth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XII), San Jose, CA, USA, Oct 2006. [pdf].

S. Narayanasamy, G. Pokam and B. Calder. BugNet: Continuously Recording Program Execution for Deterministic Replay Debugging. In Proceedings of the 32nd Annual International Symposium on Computer Architecture (ISCA 2005), Madison, Wisconsin, USA, June 2005. [pdf].

G. Pokam and F. Bodin. An Offline Approach for Whole-Program Paths Analysis using Suffix Arrays. In Proceedings of the 17th International Workshop on Languages and Compilers for Parallel Computing (LCPC 2004), West Lafayette, Indiana, USA, September 2004. [pdf].

G. Pokam and F. Bodin. Understanding the Energy-Delay Tradeoff of ILP-based Compilation Techniques on a VLIW Architecture. In Proceedings of the 11th International Workshop on Compilers for Parallel Computers (CPC 2004), Chiemsee, Germany, July 2004. [ps].

G. Pokam, O. Rochecouste, A. Seznec and F. Bodin. Speculative Software Management of Datapath-width for Energy Optimization. In Proceedings of the ACM SIGPLAN/SIGBED 2004 Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES 2004), Washington, DC, USA, June 2004. [gziped].

G. Pokam and F. Bodin. Energy-Efficiency Potential of a Phase-based Cache Resizing Scheme for Embedded Systems. In Proceedings of the 8th IEEE Annual Worskhop on Interaction between Compilers and Computer Architectures (INTERACT-8), Madrid, Spain, February 2004. [pdf].

G. Pokam, J. Simonnet and F. Bodin. A Retargetable Preprocessor for Multimedia Instructions. In Proceedings of the 9th International Workshop on Compilers for Parallel Computers (CPC 2001), Edinburgh, Scotland UK, June 2001. [gziped].

A. Froehlich, G. Pokam and W. Schroeder-Preikschat. EPOS and Myrinet: Effective Communication Support for Parallel Applications Running on Clusters of Commodity Workstations. In Proceedings of the 8th International Conference on High Performance Computing and Networking Europe (HPCN Europe 2000), Amsterdam, The Netherlands, May 2000. [gziped].

Research Reports

W. Chuang, S. Narayanasamy, G. Pokam, J. Sampson, M. Van Biesbrouck, G. Venkatesh, O. Colavin and B. Calder. Page-Based Transactional Memory to Provide Fast Virtual Transactions. UCSD Technical Report CS2005-0848, December 2005.

G. Pokam and F. Bodin. Energy Reduction Potential of a Phase-based Cache Resizing Scheme for Embedded Systems. INRIA Research Report No 5036, December 2003.

G. Pokam and F. Bodin. Energy-Delay Tradeoff Analysis of ILP-based Compilation Techniques on a VLIW Architecture. INRIA Research Report No 5026, November 2003.

Thesis

G. Pokam. Low-Power Compilation Techniques on VLIW Architectures. Ph.D. Thesis, Order Number 2995, University of Rennes 1, France, July 2004.

G. Pokam. Communication Strategies (Abstractions and Protocols) to Support Medium/Fine Grain Parallelism on SMP Workstations Clustered by High Speed Networks. Diploma Thesis, Technical University of Berlin, December 1999.