Chung-Kuan Cheng
Professor
Department of Computer Science and Engineering,
University of California, San Diego,
La Jolla, CA 92093-0404
Address for express mail:
9500 Gilman Dr., Building EBU3 Room 2130
CSE Dept., UC San Diego, La Jolla, CA 92093-0404
Email: ckcheng at ucsd dot edu,
Tel: (858) 534-6184,
Fax: (858) 534-7029
I am a Professor at the Department of Computer Science and
Engineering and an Adjunct Professor at the Department of Electrical and
Computer Engineering, the University of California, San Diego. I have served
as a Senior Engineer, Chief Scientist, and Consultant at various System,
Design, and Electronic Desgin Automation Companies. I got my Ph.D. from
the Department of Electrical Engineering and Computer Science at the University
of California, Berkeley in 1984.
Recent Photos
Star power, 2004
Annual event, 2005
Cruising in San Diego, 1/04/07
IBM EIP Award at EPEP 10/29/07
Books or Chapters
C.K. Cheng and A. Kahng, Rapid Prototyping Systems,
Wiley Encyclopedia of Electrical and Electronics Engineering,
by J. G. Webster, vol. 18, pp. 234-242, 1999.
C.K. Cheng, J. Lillis, S. Lin, N. Chang, Interconnect Analysis
and Synthesis, John-Wiley, 2000, Japanese version edited by
H. Onodera, 2003, ISBN4-563-06718-0 C3005.
C.K. Cheng, Z. Qin, and S. Tan, Symbolic Analysis and Reduction
of VLSI Circuits, Springer, 2004.
Z. Feng, B. Yao, and C.K. Cheng, Floorplan Representation in VLSI,
Handbook of DATA Structures and Applications, by D.P. Mehta and
S. Sahni, Chapman & Hall/CRC, pp. 53-1: 53-29, 2004.
Ratio Cut Package, 1989-1995
Ratio Cut Partitioning
RLC Reduction of Interconnect, 1999-2003
Y-Delta Transformation
Hurwitz Interconnect Delay Evaluation
Floorplanning of Blocks, 1999-2001
O-Tree Floorplanning
Y Architecture, 2002-2003
Physical Planning,
Y-Architecture
Yet another Y-Architecture
Surfliner, 2005
Distortionless Transmission Line
Current Research Thrusts
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Digital Circuit Analysis: All-corner static timing analysis.
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Circuit Simulation: SPICE_Diego for whole chip analysis.
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Three Dimensional Floorplanning.
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Low Power-Delay Logic Styles: Current Mode Differential Logic.
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Data Path Synthesis: Optimum prefix adders, shifters, and mutipliers.
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Interconnection Networks: Optimal topologies and wire styles.
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Interconnection Technologies: Distortionless signaling using passive compensation.
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EKG Analysis: Noninvasive arrhythmias analysis.
Honors and Awards
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NCR Best Teaching Award, School of Engineering, University of California,
San Diego, 1991.
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IEEE Circuits and Systems Society, CAD Transactions Best Paper Awards, 1997, 2002.
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IEEE Fellow, 2000.
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IBM Faculty Awards, 2004, 2006, 2007.
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Honorary Appointment as a Guest Professor of the Department of
Computer Science & Technology, Tsinghua University, 2002-2008.
Research Works in Alphabetical Order
Ancestor Tree: A generalized Gomory and Hu's Cut Tree for symmetric cut costs
(Separator Tree, sec. 8.7 in Network Flows, Ahuja, Magnanti, Orlin).
Cluster Ratio Cut: A multiway partitioning method with flexible sized
partitions.
Corner Block List: A representation for mosaic floorlanning.
O-Tree: Ordered Tree for floorplanning representation with rectangular blocks.
P-Tree: Permutation Tree for VLSI interconnect topology and buffer synthesis
(ch. 7 in C.K. Cheng, J. Lillis, S. Lin, N. Chang, Interconnect Analysis
and Synthesis, John-Wiley, 2000, Japanese version edited by
H. Onodera, 2003, ISBN4-563-06718-0 C3005).
RAMP: An analytic placement with a quadratic cost function.
Ratio Cut: Network partitioning with flexible sized bisections.
Replication Cut: Network partitioning with node replications.
SPICE_Diego: A revision of SPICE released by UCSD.
Surfliner: An interconnect circuit style for high speed and low power clock
and signal communications.
Twin Binary Tree: A floorplanning representation for mosaic floorplanning.
UPlacer: Unified Placer, A placer with a unified cost function.
Y Architecture: A non-Manhattan interconnect methodology for VLSI designs.
Generalized Wye-Delta Transformation: A generalized circuit reduction method
(ch. 4 in C.K. Cheng, Z. Qin, and S. Tan, Symbolic Analysis and Reduction
of VLSI Circuits, Springer, 2004).
Services
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Program Co-Chair, International Conf. on ASIC, ASICON, Oct. 2003.
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Program Co-Chair, ASPDAC 2004.
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Tutorial Co-Chair, ASPDAC 2005.
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President 2003-2005, San Diego Chinese American Science and Engineering Association.
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Tutorial Co-Chair, ASPDAC 2006.
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One Day Tutorial Co-Organizer, DAC 2006.
Classes
CSE291: Interconnect and Packaging
Winter 2006
CSE245: Circuit Simulation
Spring 2006
CSE246: Computer Arithmetic Algorithms and Hardware Design Fall 2006
CSE291: Interconnection Networks Winter 2007
CSE245: Circuit Simulation and Verification Spring 2008
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