1. Improved IC Design Floorplan Generation using Ceiling and Floor Contours on an O-Tree Structure filed on 6/19/99, by CK Cheng and Pei-Ning Guo, 6,282,694, 8/28/01.
2. Interconnect Delay Driven Placement and Routing of an Integrated Circuit Design, filed on 4/8/99, by CK Cheng and So-Zen Yao, 6,327,693, 12/4/01.
3. Method and Apparatus for Clock Tree Solutions Synthesis based on Design Constraints filed on 6/19/99 by CK Cheng and Jiang-Jih Chao 6,367,060, 4/2/2002.
4. Interconnection Architecture and Method of Assessing Interconnection Architecture, C.K. Cheng, R. Graham, E. Cheng, H. Chen. B. Yao, US PCT Patent Application No. US03/28620, filed on 9/9/2003 by UCSD, SD2003-028.
5. Efficient Transistor Level Simulation Using Two-Stage Newton-Raphson and Multigrid Method, CK Cheng and Zhengyong Zhu, filed by UCSD, SD2005-013.
6. Circuit Network Analysis using Algebraic Multigrid Approach, C.K. Cheng and Z. Zhu, filed by UCSD, SD2005-252.
7. Circuit Splitting in Analysis of Circuits at Transistor Level C.K. Cheng, R. Shi, and Z. Zhu, filed by UCSD, SD2005-129-PCT, June 7, 2005.
8. High Speed Clock Distribution Transmission Line Network, C.K. Cheng and H. Chen, U.S. Patent Application No. 60/573,922 filed on 5/24/2005 by UCSD, SD2004-119.
9. Electrical Signaling via Differential Transmission Line, CK Cheng and H. Chen, file by UCSD, SD2005-207, June 29, 2005.