1. C.K. Cheng and A. Kahng, Rapid Prototyping Systems, Wiley Encyclopedia of Electrical and Electronics Engineering, by J. G. Webster, vol. 18, pp. 234-242, 1999.
2. C.K. Cheng, J. Lillis, S. Lin, N. Chang, Interconnect Analysis and Synthesis, John-Wiley, 2000, Japanese version edited by H. Onodera, 2003, ISBN4-563-06718-0 C3005.
3. C.K. Cheng, Z. Qin, and S. Tan, Symbolic Analysis and Reduction of VLSI Circuits, Springer, 2004.
4. Z. Feng, B. Yao, and C.K. Cheng, Floorplan Representation in VLSI, Handbook of DATA Structures and Applications, by D.P. Mehta and S. Sahni, Chapman & Hall/CRC, pp. 53-1: 53-29, 2004.
1. C.K. Cheng and E.S. Kuh, "Module Placement Based on Resistive Network Optimi zation," IEEE Trans. on Computer-Aided Design, vol. CAD-3, pp. 218-225, July 1984.
2. C.K. Cheng, "Linear Placement Algorithms and Applications to VLSI Design," Net works, vol. 17, pp. 439-464, Winter 1987.
3. C.K. Cheng and T.C. Hu, "Maximum Concurrent Flow and Minimum Ratio Cut," Algorithmica, vol. 8, pp. 233-249, 1992.
4. C.K. Cheng and T.C. Hu, "Ancestor Tree for Multi-Terminal Cut Functions," Tech. Report no. CS89-148, Univ. of California, San Diego, July 1989, Annals of Opera tions Research, vol. 33, pp. 199-213, 1991.
5. C.K. Cheng, D.N. Deutsch, C. Shohara, M. Taparauskas and M. Bubien, "Geometric Compaction on Channel Routing," IEEE Trans. on Computer-Aided Design, vol. 11, pp. 115-127, Jan. 1992.
6. C.K. Cheng, S.Z. Yao and T.C. Hu, "The Orientation of Modules Based on Graph Decompositions," IEEE Trans. on Computers, vol. 40, pp. 774-780, June 1991.
7. Y.C. Wei and C.K. Cheng, "Ratio Cut Partitioning for Hierarchical Designs," IEEE Trans. on Computer-Aided Design, vol. 10, pp. 911-921, July 1991.
8. C.K. Cheng and Y.C. Wei, "An Improved Two-Way Partitioning Algorithm with Stable Performance," IEEE Trans. on Computer-Aided Design, pp. 1502-1511, December 1991.
9. Y.C. Wei, C.K. Cheng and Z. Wurman, "Multiple Level Partitioning: An Applica tion to The Very Large Scale Hardware Simulators," IEEE Journal of Solid State Circuits, vol. 26, pp. 706-716, May 1991.
10. C.K. Cheng, X. Deng, Y.Z. Liao and S.Z. Yao, "Symbolic Layout Compaction under Conditional Design Rules," IEEE Trans. on Computer-Aided Design, vol. 11, pp. 475-486, April 1992.
11. C.K. Cheng "The Optimal Partitioning of Networks," Networks, vol. 22, pp. 297- 315, 1992.
12. T. Hamada, C.K. Cheng and P. Chau, "An Efficient Multi-Level Placement Tech nique Using Hierarchical Partitioning," IEEE Trans. on Circuits and Systems, vol. 39, pp. 432-439, June 1992.
13. C. Yeh, C.K. Cheng, and T.T. Lin, "A General Purpose Multiple Way Partitioning Algorithm," IEEE Trans. on CAD, vol. 13, pp. 1480-1488, Dec. 1994.
14. R. Carden and C.K. Cheng, "A Global Router with a Theoretical Bound on the Optimal Solution," IEEE Trans. on CAD, pp. 208-216, Feb. 1996.
15. C. Yeh, L.T. Liu, C.K. Cheng, T.C. Hu, S. Ahmed, and M. Liddel "Block-Oriented Programmable Design with Switching Network Interconnect," IEEE Trans. on VLSI Systems, pp. 45-53, March 1994.
16. S.Z. Yao, N.C. Chou, C.K. Cheng, and T.C. Hu "A Multi-Probe Approach for MCM Substrate Testing," IEEE Trans. on Computer-Aided Design, vol. 13, pp. 110-121, Jan. 1994.
17. C. Yeh, C. K. Cheng and T. T. Lin, "Optimization by Iterative Improvement: An Experimental Evaluation on Two-Way Partitioning," IEEE Trans. on CAD, pp. 145-153, Feb. 1995.
18. C. Yeh, C. K. Cheng and T. T. Lin, "Circuit Clustering Using A Stochastic Flow Injection Method," IEEE Trans. on CAD, pp. 154-162, Feb. 1995.
19. N. C. Chou and C. K. Cheng, "On General Zero-Skew Clock Net Construction," IEEE Trans. on VLSI Systems, pp. 141-146, March 1995.
20. N. C. Chou, C. K. Cheng, and T. Russell, "Dynamic Probe Scheduling Optimization for MCM Substrate Test," IEEE Trans. on Components, Hybrids, and Manufactur ing Tech., pp. 182-189, May 1994.
21. S. Z. Yao, C. K. Cheng, D. Dutt, S. Nahar, and C. Y. Lo, "A Cell-Based Hierarchi cal Pitchmatching Compaction Using Minimal LP," IEEE Trans. on CAD, pp. 523- 526, April 1995.
22. D. Zaleta, J. Fan, B.C. Kress, S.H. Lee, and C. K. Cheng, "Optimum Placement for Optoelectronic MultiChip Modules and the Synthesis of Diffractive Optics for Mul tichip Module Interconnects", Applied Optics, pp. 1444-1456, March 1994.
23. L.T. Liu, M.T. Kuo, C.K. Cheng, and T.C. Hu, "A Replication Cut for Two-Way Partitioning," IEEE Trans. on CAD, pp. 623-630, May 1995.
24. J. Fan, D. Zaleta, C.K. Cheng, and S.H. Lee, "Physical Models and Algorithms for Optoelectronic MCM Layout," IEEE Trans. on VLSI Systems, pp. 124-135, March 1995.
25. N.C. Chou, L.T. Liu, C.K. Cheng, W.J. Dai, and R. Lindelof, "Local Ratio Cut and Set Covering Partitioning for Huge Logic Emulation Systems," IEEE Trans. on CAD, pp. 1085-1092, Sept. 1995.
26. R. Carden and C.K. Cheng, "Early Feasibility and Cost Assessment for MCM Tech niques," Special Issue on High Performance CAD for Packaging and MCMs, Int. Journal of High Speed Electronics and Systems, vol. 6, no. 3, pp. 441-458, 1995.
27. R.J. Carragher, C.K. Cheng, X.M. Xiong, M. Fujita, and R. Paturi, "Solving the Net Matching Problem in High-Performance Chip Design," IEEE Trans. on CAD, pp. 902-911, Aug. 1996.
28. L.T. Liu, M. Shih, J. Lillis, and C.K. Cheng "Data Flow Partitioning for Clock Period and Latency Minimization," IEEE Trans. on CAS, Part I, pp. 210-220, March 1997.
29. J. Lillis, C.K. Cheng, and T.T. Lin, "Optimal Wire Sizing and Buffer Insertion for Low Power and a Generalized Delay Model," IEEE Journal of Solid State Circuits, pp. 437-447, March 1996.
30. T. Hamada, C.K. Cheng, and P. Chau, "A Wire Length Estimation Technique Utilizing Neighborhood Density Equations," IEEE Trans. on CAD, pp. 912-922, Aug. 1996.
31. C.C. Tsai, D.Y. Kao, and C.K. Cheng, "Performance Driven Bus Buffer Insertion," IEEE Trans. on CAD, pp. 429-437, April 1996.
32. X. Hong, T. Xue, J. Huang, C.K. Cheng, and E.S. Kuh, "Tiger: An Efficient Timing-Driven Global Router for Gate Array and Standard Cell Layout Design," ACM/IEEE Design Automation Conf., pp. 177-181, June 1993.
33. J. Li and C.K. Cheng, "Routability Improvement Using Dynamic Interconnect Architecture," IEEE Trans. on VLSI, pp. 498-501, September 1998.
34. J. Xu, P.N. Guo, and C.K. Cheng, " Sequence-Pair Approach for Rectilinear Module Placement, " IEEE Trans. on CAD, pp. 484-493, April 1999.
35. J. Xu, P.N. Guo, and C.K. Cheng, " Empirical Study of Block Placement by Cluster Refinement," VLSI Design, vol. 10, no. 1, pp. 71-86, 1999.
36. J. Lillis and C.K. Cheng, " Timing Optimization for Multisource Nets: Characterization and Optimal Repeater Insertion, " IEEE Trans. on CAD, pp. 322-331, March, 1999.
37. S. Chen and C.K. Cheng, " Tutorial on VLSI Partitioning, " VLSI Design, pp. 175-218, vol. 11, no. 3, 2000.
38. P.N. Guo, T. Takahashi, C.K. Cheng, and T. Yoshimura, " Floorplanning using a Tree Representation, " IEEE Trans. on CAD, pp. 281-289, Feb. 2001.
39. X.D. Yang, C.K. Cheng, W.H. Ku, and R.J. Carragher, " Reduced Order Modeling for RLC Interconnect using Hurwitz Polynomials, " IEEE Journal of Analog Integrated Circuits and Signal Processing, vol. 31, no.3, pp. 193-208, June 2002.
40. C.K. Cheng, A.B. Kahng, B. Liu, and D. Stroobandt, "Toward Better Wireload Models in the Presence of Obstacles," IEEE Trans. on VLSI, pp. 177-189, April 2002.
41. B. Yao, H. Chen, C.K. Cheng, and R. Graham, "Floorplan Representations: Complexity and Connections," ACM Trans. on Design Automation of Electronic Systems, vol. 8, pp. 55-80, Jan. 2003.
42. T. Jing, X. Hong, J. Xu, H. Bao, C.K. Cheng, and J. Gu, "UTACO: A Unified Timing and Congestion Optimization Algorithm for Standard Cell Global Routing," IEEE Trans. on CAD, pp. 358-365, March 2004.
43. X. Wu, X. Hong, Y. Cai, Z. Luo, C.K. Cheng, J. Gu, and W. Dai, "Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques," IEEE Trans. on CAD, pp. 1086-1094, July 2004.
44. T. Takahashi, P.N. Guo, C.K. Cheng, and T. Yoshimura, "Floorplanning using a Tree Representation: A Summary," IEEE Circuits and Systems Magazine, pp. 26-29, vo. 3, no. 2, 2003.
45. C.W. Chang, M.F. Hsiao, B. Hu, K. Wang, M. Marek-Sadowska, C.K. Cheng, and S.J. Chen, "Fast Postplacement Optimization Using Functional Symmetries," IEEE Trans. on Computer-Aided Design, pp. 102-118, Jan. 2004.
46. H. Chen, C.K. Cheng, A.B. Kahng, I. Mandoiu, Q. Wang and B. Yao, "The Y-Architecture for On-Chip Interconnect: Evaluations and Methodologies," IEEE Trans. on Computer Aided Design, pp. 588-599, April 2005.
47. Y. Ma, X. Hong, S. Dong, S. Chen, C.K. Cheng, and J. Gu, "Buffer Planning as an Integral Part of Floorplanning with Consideration of Routing Congestion," IEEE Trans. on Computer Aided Design, pp. 609-621, April 2005.
48. Z. Zhu, H. Peng, K. Rouz, M. Borah, C.K. Cheng and E.S. Kuh, "Two-Stage Newton-Raphson Method for Transistor Level Simulation," IEEE Trans. on Computer Aided Design, pp. 881-895, May 2007.
49. S. Zhou, B. Yao, H. Chen, Y. Zhu, M. Hutton, T. Collins, S. Srinivasan, N. Chou, P. Suaris, and C.K. Cheng, "Efficient Timing Analysis with Known False Paths Using Biclique Covering," IEEE Trans. on Computer Aided Design, pp. 959-969, May 2007.
50. H. Zhu, C.K. Cheng, and R. Graham, "On the Construction of Zero-Deficiency Parallel Prefix Adder with Minimum Depth," ACM Trans. on Design Automation of Electronic Systems, pp. 387-409, 2006.
51. Z. Li, X. Hong, Q. Zhou, Y. Cai, J. Bian, H.H. Yang, V. Pitchumani, and C.K. Cheng, "Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization," IEEE Trans. on Circuits and Systems, pp. 2637-2646, Dec. 2006.
1. C.K. Cheng and E.S. Kuh, "Partitioning and Placement Based on Network Optimi zation," IEEE Int. Conf. on Computer-Aided Design, pp. 86-88, 1983.
2. J.T. Li, C.K. Cheng, M. Turner, E.S. Kuh and M. Marek-Sadowska, "Automatic Layout of Gate Arrays," Custom Integrated Circuits Conf., pp. 518-521 May 1984.
3. C.K. Cheng, "Decomposition Algorithms for Linear Placement and Applications to VLSI Design," IEEE Int. Symposium on Circuits and Systems, pp. 1047-1050, June 1985. 4. C.K. Cheng and D.N. Deutsch, "Improved Channel Routing by Via Minimization and Shifting," ACM/IEEE Design Automation Conf., pp. 677-680, June 1988.
5. Y.C. Wei and C.K. Cheng, "Towards Efficient Hierarchical Designs by Ratio Cut Partitioning," IEEE Int. Conf. on Computer-Aided Design, pp. 298-301 Nov. 1989.
6. C.K. Cheng and T.C. Hu, "Ancestor Tree for Arbitrary Multi-Terminal Cut Func tions," Integer Programming/Combinatorial Optimization Conf., Univ. of Waterloo, pp. 115-127, May 1990.
7. C.K. Cheng, T.C. Hu and S.Z. Yao "The Modular Orientation of VLSI Layout," IEEE Symp. on Circuits and Systems, pp. 1600-1603, May 1990.
8. Y.C. Wei and C.K. Cheng, "A Two-Level Two-Way Partitioning Algorithm," IEEE Int. Conf. on Computer-Aided Design, pp. 516-519, Nov. 1990.
9. C.K. Cheng, "The Optimal Circuit Decompositions Using Network Flow Formula tions," IEEE Int. Symp. on Circuits and Systems, pp. 2650-2653, May 1990.
10. R. Carden and C.K. Cheng, "A Global Router Using An Efficient Approximate Multicommodity Multiterminal Flow Algorithm," ACM/IEEE Design Automation Conf., pp. 316-321, July 1991.
11. C. Yeh, C.K. Cheng and T.T. Lin, "A General Purpose Multiple Way Partitioning Algorithm," ACM/IEEE Design Automation Conf., pp. 421-426, July 1991. The paper is nominated for the best paper award (15 out of 454 papers).
12. C.K. Cheng, Y.C. Wei and Z. Wurman "The Mapping of Logic Designs into A Very Large Scale Hardware Simulator," IEEE Int. Symp. on Circuits and Systems, pp. 2036-2039, June 1991.
13. T. Hamada, C.K. Cheng and P. Chau, "An Efficient Multi-Level Placement Tech nique Using Hierarchical Partitioning," IEEE Int. Symp. on Circuits and Systems, pp. 2044-2047, June 1991.
14. C.K. Cheng, X. Deng, Y.Z. Liao and D. Yao, "Discussion on VLSI Layout Com paction with Conditional Constraints," IEEE Int. Symp. on Circuits and Systems, pp. 2132-2135, June 1991.
15. R. Carden, and C.K. Cheng, "Feasibility Estimation and Cost Optimization for Mul tichip Module Technologies," IEEE Int. Conf. on ASIC, P9:1.1-4, Sept. 1991.
16. S.Z. Yao, N.C. Chou, C.K. Cheng and T.C. Hu, "A Multi-Chip Module Substrate Testing Algorithm," IEEE Int. Conf. on ASIC, P9:4.1-4, Sept. 1991.
17. C.W. Yeh, C.K. Cheng, and T.T. Lin, "An Experimental Evaluation of Partitioning Algorithms," IEEE Int. Conf. on ASIC, P14:1.1-4, Sept. 1991.
18. T. Hamada, C.K. Cheng and P. Chau "A Wire Length Estimation Technique Utiliz ing Neighborhood Density Equations," ACM/IEEE Design Automation Conf., pp. 57-61, July 1992.
19. X.L. Hong, J. Huang, C.K. Cheng, and E.S. Kuh, "FARM: An Efficient Feedthrough Pin Assignment Algorithm," ACM/IEEE Design Automation Conf., pp. 530-535, July 1992.
20. C.W. Yeh, L.T. Liu, C.K. Cheng, T.C. Hu, S. Ahmed, and M. Liddel, "Block Oriented Programmable Design with Switching Network Interconnect," Synthesis and Simulation Meeting and International Interchange, Kobe, Japan, pp. 406-414, April 1992.
21. J.W. Chung, R. Carragher, C.K. Cheng, and X.M. Xiong, "Performance Driven Routing Algorithms for Electronic Interconnects," International Workshop on Lay out Synthesis, vol. 2., pp. 155-156, May 1992.
22. N.C. Chou, C.K. Cheng, and T.C. Russell, "High Performance Microelectronic Sub strate Verification Using Probe Testers," IEEE Int. Conf. on ASIC, pp. 230-233, Sept. 1992.
23. S.Z. Yao, N.C. Chou, C.K. Cheng, and T.C. Hu, "An Optimal Probe Testing Algo rithm for The Connectivity Verification of MCM Substrates," IEEE Int. Conf. on Computer-Aided Design, pp. 264-267, Nov. 1992.
24. C.W. Yeh, C.K. Cheng, and T.T. Lin, "A Probabilistic Multicommodity-Flow Solu tion to Circuit Clustering Problems," IEEE Int. Conf. on Computer-Aided Design, pp. 428-431, Nov. 1992.
25. R. Carragher, C.K. Cheng, and X.M. Xiong, "The Net Matching Problem in High Performance Microelectronics Design," ACM/SIGDA Physical Design Workshop, pp. 52-62, April 1993.
26. J. Fan, D. Zaleta, C.K. Cheng, and S.H. Lee, "Physical Layout Algorithms for Com puter Generated Holograms in Optoelectronic MCM Systems Design," IEEE Mul tichip Module Conf., pp. 198-203, March 1993.
27. S.H. Lee, V.H. Ozguz, J. Fan, D. Zaleta, and C.K. Cheng, "Computer Aided Design and Packaging Optoelectronic Systems with Free Space Optical Interconnects," IEEE Custom Integrated Circuits Conf., 29.3.1-4, May 1993.
28. X.M. Xiong, J. Hardin, and C.K. Cheng, "PAS: A Stand Alone Placement Annota tion System for High Speed Designs," IEEE Custom Integrated Circuits Conf., pp. 9.1.1-5, May 1993.
29. T. Hamada, C.K. Cheng, and P. Chau, "PRIME: A Timing-Driven Placement Using A Piecewise Linear Resistive Network Approach," ACM/IEEE Design Automation Conf., pp. 531-536, June 1993.
30. J. Huang, X. Hong, C.K. Cheng, and E.S. Kuh, "An Efficient Timing-Driven Global Routing Algorithm," ACM/IEEE Design Automation Conf., pp. 596-600, June 1993.
31. S.Z. Yao, C.K. Cheng, D. Dutt, S. Nahar, and C.Y. Lo, "Cell-Based Hierarchical Pitchmatching Compaction Using Minimal LP," ACM/IEEE Design Automation Conf., pp. 395-400, June 1993. The paper is nominated for the best paper award (15 out of 453 papers).
32. X. Hong, T. Xue, C.K. Cheng, E.S. Kuh, and J. Huang "Performance-Driven Steiner Tree Algorithms for Global Routing," ACM/IEEE Design Automation Conf., pp. 177-181, June 1993.
33. N.C. Chou and C.K. Cheng, "Performance-Driven Clock Net Routing," Int. Conf. on CAD/Graphics, Beijing, China, pp. 429-434, Aug. 1993.
34. R.J. Carragher, C.K. Cheng, and X.M. Xiong, "The Net Matching Problem in High Performance Microelectronics Design," Int. Conf. on CAD/Graphics, Beijing, China, pp. 546-551, Aug. 1993.
35. J. Fan, S.H. Lee, C.K. Cheng, and T. Hamada, "Free Space Optoelectronic System Placement Based on Quadratic Approximation," Int. Conf. on CAD/Graphics, Beij ing, China, pp. 493-499, Aug. 1993.
36. N.C. Chou and C.K. Cheng, "Wire Length and Delay Minimization in General Clock Net Routing," IEEE Int. Conf. on Computer-Aided Design, pp. 552-555, Nov. 1993.
37. R. Carragher, C.K. Cheng, and M. Fujita, "An Efficient Algorithm for the Net Matching Problem," IEEE Int. Conf. on Computer-Aided Design, pp. 640-644, Nov. 1993.
38. L.T. Liu, M. Shih, N.C. Chou, C.K. Cheng, and W. Ku, "Performance-Driven Parti tioning Using Retiming and Replication," IEEE Int. Conf. on Computer-Aided Design, pp. 296-299, Nov. 1993.
39. X.M. Xiong and C.K. Cheng "Interconnect and Output Driver Modeling of High Speed Designs," IEEE Int. Conf. on ASIC, pp. 507-510, Sept. 1993.
40. R.R. McBride, J. Chung, E.C. Shi, and C.K. Cheng "Pin Redistribution for Mul tichip Module Designs," Int. Symp. on Microelectronics, pp. 605-609, Nov. 1993.
41. N.C. Chou and C.K. Cheng "Optimal Test Size and Efficient Probe Scheduling for Substrate Verification Using Two-Probe Testers," Int. Symp. on Microelectronics, pp. 276-281, Nov. 1993.
42. R. Carragher, N.C. Chou, C.K. Cheng, T. Russell "Distortion Mapping for Cofired Ceramic Substrate Testing," Int. Symp. on Microelectronics, pp. 295-300, Nov. 1993.
43. R. Carragher and C.K. Cheng "Minimizing and Balancing Delay Using Fanout Tree Buffering and Gate-Sizing," Synthesis and Simulation Meeting and International Interchange, pp. 337-344, Oct. 1993.
44. H.Y. Liou, T.T. Lin, L.T. Liu, and C.K. Cheng, "Circuit Partitioning for Pipelined Pseudo-Exhaustive Testing Using Simulated Annealing," IEEE Custom Integrated Circuits Conf., pp. 417-420, May 1994.
45. L.T. Liu, M. Shih, and C.K. Cheng, "Data Flow Partitioning for Clock Period and Latency Minimization," ACM/IEEE Design Automation Conf., pp. 658-663, June 1994.
46. N.C. Chou, L.T. Liu, C.K. Cheng, W.J. Dai, and R. Lindelof, "Circuit Partitioning for Huge Logic Emulation Systems," ACM/IEEE Design Automation Conf., pp. 244-249, June 1994.
47. J. Chung and C.K. Cheng, "Optimal Buffered Clock Tree Synthesis," IEEE ASIC Conf., pp. 130-133, Sept. 1994.
48. H.Y. Liou, T.T. Lin, and C.K. Cheng, "A Study of Pipelined Pseudo-Exhaustive Testing on VLSI Circuits with Feedback," IEEE ASIC Conf., pp. 421-425, Sept. 1994.
49. J. Chung and C.K. Cheng, "Skew Sensitivity Minimization of Buffered Clock Tree," IEEE ICCAD Conf., pp. 280-283, Nov. 1994.
50. L.T. Liu, M.T. Kuo, C.K. Cheng, and T.C. Hu, "Performance-Driven Partitioning Using A Replication Graph Approach," ACM/IEEE Design Automation Conf., June 1995, pp. 206-210.
51. M.T. Kuo, L.T. Liu, and C.K. Cheng, "Finite State Machine Decomposition for I/O Minimization," IEEE Int. Symp. on Circuits and Systems, pp. 1061-1064, May 1995.
52. J. Lillis, C.K. Cheng, and T.T. Lin, "Optimal and Efficient Buffer Insertion and Wire Sizing," IEEE Custom Integrated Circuits Conf., May 1995, pp. 259-262.
53. J. Chung, D. Kao, C.K. Cheng, and T.T. Lin, "Optimization Of Power Dissipation And Skew Sensitivity In Clock Buffer Synthesis" Int. Symp. on Low Power Design, pp. 179-184, April 1995.
54. J. Li and C.K. Cheng, "Routability Improvement Using Dynamic Interconnect Architecture," IEEE FPGAs for Custom Computing Machines, April 1995.
55. M.T. Kuo, L.T. Liu, and C.K. Cheng, "Finite State Machine Partitioning for I/O Limited Design," Int. Symp. on VLSI Technology, Systems, and Applications, May 1995.
56. R.J. Carragher, M. Fujita, and C.K. Cheng, "Simple Tree-Construction Heuristics for the Fanout Problem," Proc. of the 1995 ACM/IEEE International Workshop on Logic Synthesis, Tahoe City, CA., May 23-26, 1995, pp. 1-11 -- 1-22, International Conference on Computer Design, October 1995.
57. L.T. Liu, M.T. Kuo, S.C. Huang, "A Gradient Method of the Initial Partition of Fiduccia-Mattheyses Algorithm," IEEE/ACM Int. Conf. on Computer-Aided Design, Nov. 1995, pp. 229-234.
58. J. Li, J. Lillis, and C.K. Cheng, "Linear Decomposition Algorithmm for VLSI Design Applications," IEEE/ACM Int. Conf. on Computer-Aided Design, Nov. 1995, pp. 223-228.
59. J. Lillis, C.K. Cheng, and T.T. Lin, "Optimal Wire Sizing and Buffer Insertion for Low Power and a Generalized Delay Model," IEEE/ACM Int. Conf. on Computer Aided Design, Nov. 1995, pp. 138-143.
60. C.C. Tsai, C.K. Cheng, D.Y. Kao, and T.T. Lin, "Performance Driven Multiple Sources Bus Synthesis Using Buffer Insertion," ASP/DAC Aug. 1995, pp. 273-278, Chiba, Japan.
61. C.K. Cheng, "Rapid Prototyping Systems using Field Programmable Devices," invited paper, VLSI/CAD workshop, Taiwan, Aug. 17-19, 1995.
62. D.Y. Kao, C.C. Tsai, C.K. Cheng, and T.T. Lin, "New Design and Implementation for Singal Repeaters," VLSI/CAD workshop, Taiwan, pp. 173-176, Aug. 17-19, 1995.
63. J. Li, J. Lillis, L.T. Liu, and C.K. Cheng, "New Spectral Linear Placement and Clustering Approach, " ACM/IEEE Design Automation Conf., June 1996, pp. 88-93.
64. M.T. Kuo, L.T. Liu, and C.K. Cheng, " Network Partitioning into Tree Hierarchies, " ACM/IEEE Design Automation Conf., June 1996, pp. 477-482.
65. J. Lillis, C.K. Cheng, T.T. Lin, and C.Y. Ho, " New Performance Driven Routing Techniques with Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing," " ACM/IEEE Design Automation Conf., June 1996, pp. 395-400.
66. H.Y. Liou, T.T. Lin, and C.K. Cheng, " Area Efficient Pipelined Pseudo-Exhaustive Testing with Retiming," " ACM/IEEE Design Automation Conf., June 1996, pp. 274-279.
67. J. Lillis, C.K. Cheng, and T.T. Lin, " Algorithms for Optimal Introduction of Redundant Logic for Timing and Area Optimization, Int. Symp. on Circuits and Systems, 1996.
68. J. Lillis, C.K. Cheng, and T.T. Lin, " Smultaneous Routing and Buffer Insertion for High Performance Interconnect, " IEEE Great Lakes Symp. on VLSI, March 1996, pp. 148-153.
69. M.T. Kuo, Y. Wang, C.K. Cheng, and M. Fujita, " BDD-Based Logic Partitioning for Sequential Circuits, " ASP/DAC Jan. 1997, pp. 607-612, Chiba, Japan.
70. F. Liu, J. Lillis, and C.K. Cheng, " A New Layout-Driven Timing Model for Incremental Layout Optimization, " ASP/DAC Jan. 1997, pp. 127-131, Chiba, Japan.
71. J. Dufour, R. McBride, P. Zhang, and C.K. Cheng, " A Custom Cell Placement Tool, ASP/D" AC Jan. 1997, pp. 271-276, Chiba, Japan.
72. J. Lillis and C.K. Cheng, " Timing Optimization for Multi-Source Nets: Characterization and Optimal Repeater Insertion, " ACM/IEEE Design Automation Conf., pp. 214-219, June 1997.
73. J. Xu, P.N. Guo, and C.K. Cheng " Cluster Refinement for Block Placement, " ACM/IEEE Design Automation Conf., pp. 762-765, June 1997.
74. M.T. Kuo and C.K. Cheng " A New Network Flow Approach for Hierarchical Tree Partitioning, " ACM/IEEE Design Automation Conf., pp. 512-517, June 1997.
75. F.J. Liu, J. Lillis, and C.K. Cheng, " Design and Implementation of a Global Router Based on a New Layout Driven Timing Model with Three Poles, " IEEE Int. Symp. on Circuits and Systems, 1997.
76. J. Xu, P.N. Guo, and C.K. Cheng, " Rectilinear Block Placement using Permutation Pair, " Int. Symp. of Physical Design, April 1998.
77. F.J. Liu and C.K. Cheng, " Extending Moment Computation to 2-Port Circuit Representations, " ACM/IEEE Design Automation Conf., pp. 473-476, June 1998.
78. D. Wang, P. Zhang, C.K. Cheng, and A. Sen, " A Performance-Driven I/O Pin Routing Algorithm, " Asia and South Pacific Design Automation Conf., Hong Kong, Jan. 1999.
79. P.N. Guo, C.K. Cheng, and T. Yoshimura, " An O-Tree Representation of Nonslicing Floorplan and Its Applications, " ACM/IEEE Design Automation Conf., pp. 268-273, June 1999.
80. X. Yang, W. Ku, and C.K. Cheng, " RLC Interconnect Delay Estimation via Moments of Amplitude and Phase Response, " IEEE/ACM Int. Conf. on Computer-Aided Design, Nov. 1999, pp. 208-213.
81. X. Yang, C.K. Cheng, and W. Ku, " A New Efficient Simulation Method for RLC Interconnect via Amplitude and Phase Approximation, " ASP/DAC Jan. 2000, Yokohoma, Japan.
82. Y. Pang, C.K. Cheng, and T. Yoshimura, " An Enhanced Perturbing Algorithm for Floorplan Design using O-tree Representation, " Symp. Physical Design, pp. 168-173, April 2000.
83. Y. Pang, F. Balasa, K.V. Lampaert, and C.K. Cheng, " Block Placement with Symmetry Constraints based on the O-tree Non-Slicing Representation, " IEEE/ACM Design Automation Conf., pp. 464-467, June 2000.
84. C.W. Chang, C.K. Cheng, P. Suaris, and M. Marek-Sadowska, " Fast Post-Placement Rewiring using Easily Detectable Functional Symmetries, " IEEE/ACM Design Automation Conf., pp. 286-289, June 2000.
85. X.D. Yang, C.K. Cheng, W.H. Ku, and R.J. Carragher, " Hurwitz Stable Reduced Order Modeling for RLC Interconnect, " Int. Conf. Computer-Aided Design, Nov. 2000, pp. 222-228.
86. X. Hong, G. Huang, Y. Cai, J. Gu, S. Dong, C.K. Cheng, and J. Gu, " Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan, " Int. Conf. Computer-Aided Design, Nov. 2000, pp. 8-12.
87. C.K. Cheng, A.B. Kahng, B. Liu, and D. Stroobandt, " Toward Better Wireload Models in the Presence of Obstacles, " Asia South Pacific Design Automation Conf., Jan. 2001, pp. 527-532.
88. C.K. Cheng, " Timing Closure using Layout Based Design Process, " Second Online Symp. for Electronics Engineers, http://www.techonline.com/osee/, Feb. 2001.
89. B. Yao, H. Chen, C.K. Cheng, and R. Graham, " Revisiting Floorplan Representations, " Int. Symp. on Physical Design, 2001, pp. 138-143.
90. S. Zhou, S. Dong, X. Hong, Y. Cai, J. Gu, and C.K. Cheng " ECBL: An Extended Corner Block List with O(n) Complexity and Solution Space Including Optimum Placement, " Int. Symp. on Physical Design, 2001, pp. 150-155.
91. Y. Pang, K. Lampert, C.K. Cheng, and W. Xie, " Rectilinear Block Packing Using O-tree Representation, " Int. Symp. on Physical Design, 2001, pp. 156-161.
92. Y. Ma, X. Hong, S. Dong, Y. Cai, C.K. Cheng, and J. Gu, " Floorplanning with Abutment Constraints and L-Sahped/T-Shaped Blocks Based on Corner Block List, " ACM/IEEE Design Automation Conf. 2001.
93. Y. Ma, S. Dong, X. Hong, Y. Cai, C.K. Cheng, and J. Gu, "VLSI Floorplanning with Boundary Constraints Based on Corner Block List," Asia South Pacific Design Automation Conf., Jan. 2001, pp. 509-512.
94. Z. Qin, Z. Zhu, and C.K. Cheng, "Efficient Transient Analysis for Large Linear Networks," SASIMI Oct. 2001, pp 293-300.
95. X. Wu, X. Hong, Y. Cai, C.K. Cheng, J. Gu, and W. Dai, "Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques," Int. Conf. Computer-Aided Design, Nov. 2001.
96. H. Chen, C. Qiao, F. Zhou, and C.K. Cheng, "Refined Single Trunk Tree: A Rectilinear Steiner Tree Generator for Interconnect Prediction," Int. Workshop on System Level Interconnect Prediction, pp. 85-90, April 2002.
97. E.Y. Cheng, F. Zhou, B. Yao, C.K. Cheng, and R. Graham, "Balancing the Interconnect Topology for Arrays of Processors between Cost and Power," IEEE Int. Conf on Computer Design, pp. 30-35, Sept. 2002.
98. H. Chen, B. Yao, F. Zhou, and C.K. Cheng, "Physical Planning of On-Chip Interconnect Architectures," IEEE Int. Conf on Computer Design, pp. 180-186, Sept. 2002.
99. H. Chen, B. Yao, F. Zhou, and C.K. Cheng, "The Y-Architecture: Yet Another On-Chip Interconnect Solution," Asia South Pacific Design Automation Conf., pp. 840-846, Jan. 2003.
100. Z. Qin, and C.K. Cheng, "RCLK-VJ Network Reduction With Hurwitz Polynomial Approximation," Asia South Pacific Design Automation Conf., pp. 283-291, Jan. 2003.
101. S. Chen, X. Hong, S. Dong, Y. Ma, Y. Cai, C.K. Cheng, and J. Gu, "A Buffer Planning Algorithm Based on Dead Space Redistribution," Asia South Pacific Design Automation Conf., pp. 435-438, Jan. 2003.
102. T. Jing, X. Hong, Y. Cai, J. Xu, C.K. Cheng, and J. Gu, "UTACO: A Unified Timing and Congestion Optimization Algorithm for Standard Cell Global Routing," Asia South Pacific Design Automation Conf., pp. 834-839, Jan. 2003.
103. H. Chen, C.K. Cheng, A.B. Kahng, I. Mandoiu, and Q. Wang, "Estimation of Wirelength Reduction for lambda-Geometry vs. Manhattan Placement and Routing," Int. Workshop on System Level Interconnect Prediction, pp. 71-76, April 2003.
104. F. Zhou, E.Y. Cheng, B. Yao, C.K. Cheng, and R. Graham, "A Hierarchical Three-Way Interconnect Architecture for Hexagonal Processors," Int. Workshop on System Level Interconnect Prediction, pp. 133-139, April 2003.
105. Y. Ma, X. Hong, S. Dong, S. Chen, Y. Cai, C.K. Cheng, and J. Gu, "An Integrated Floorplanning with an Efficient Buffer Planning Algorithm," Int. Symp. Physical Design, pp. 136-142, April 2003.
106. Z. Qin and C.K. Cheng, "Realizable Parasitic Reduction Using Generalized Y-Delta Transformation, ACM/IEEE Design Automation Conference, pp. 220-225, June 2003.
107. Z. Zhu, B. Yao, and C.K. Cheng, "Power Network Analysis Using an Adaptive Algebraic Multigrid Approach, ACM/IEEE Design Automation Conference, pp. 105-108, June 2003.
108. H. Chen, C.K. Cheng, N.C. Chou, A.B. Kahng, J.F. MacDonald, P. Suaris, B. Yao, and Z. Zhu, "An Algebraic Multigrid Solver for Analytical Placement with Layout Based Clustering, ACM/IEEE Design Automation Conference, pp. 794-799, June 2003.
109. Y. Ma, X. Hong, S. Dong, S. Chen, Y. Cai, C.K. Cheng, and J. Gu, "Dynamic Global Buffer Planning Optimization Based on Detail Block Locating and Congestion Analysis," ACM/IEEE Design Automation Conference, pp. 806-811, June 2003.
110. J. Liu, S. Zhou, H. Zhu, K.T. Tseng, and C.K. Cheng "Optimal Parallel-Prefix Adders using a Dynamic Programming Algorithm," Int. Workshop on Logic and Synthesis, May 2003, pp. 113-119.
111. H. Chen, C.K. Cheng, A.B. Kahng, I. Mandoiu, and Q. Wang, "The Y-Architecture for On-Chip Interconnect: Analysis and Methodology," IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 13-19, 2003.
112. J. Liu, S. Zhou, H. Zhu, C.K. Cheng "An Algorithmic Approach for Generic Parallel Adders," IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 734-740, 2003.
113. Y. Ma, X. Hong, S. Dong, S. Chen, Y. Cai, C.K. Cheng, and J. Gu, "Buffer Allocation Algorithm with Consideration of Routing Congestion," Asia and South Pacific Design Automation Conf., pp. 621-623, 2004.
114. M. Mori, H. Chen, B. Yao, and C.K. Cheng, "A Multiple Level Network Approach for Clock Skew Minimization with Process Variations," Asia and South Pacific Design Automation Conf., pp. 263-268, 2004.
115. H. Chen, C.K. Cheng, A.B. Kahng, M. Mori, and Q. Wang, "Optimal Planning for Mesh-Based Power Distribution," Asia and South Pacific Design Automation Conf., pp. 444-449, 2004.
116. S. Chen, X. Hong, S. Dong, Y. Ma, Y. Cai, C.K. Cheng, and J. Gu, "A Buffer Planning Algorithm with Congestion Optimization," Asia and South Pacific Design Automation Conf., pp. 615-620, 2004.
117. H. Zhu, R. Graham, and C.K. Cheng, "Constructing Zero-deficiency Parallel Prefix Adder of Minimum Depth," Asia and South Pacific Design Automation Conf., pp. 883-888, 2005.
118. S. Zhou, B. Yao, J. Liu, and C.K. Cheng, "Integrated Algorithmic Logical and Physical Design of Integer Multiplier," Asia and South Pacific Design Automation Conf., pp. 1014-1017, 2005.
119. H. Chen, C.K. Cheng, "A Multi-Level Transmission Line Network Approach for Multi-Giga Hertz Clock Distribution," Asia and South Pacific Design Automation Conf., pp. 103-106, 2005.
120. Z. Zhu, K. Rouz, M. Borah, C.K. Cheng, and E.S. Kuh "Efficient Transient Simulation for Transistor-Level Analysis," Asia and South Pacific Design Automation Conf., 240-243, 2005.
121. R. Shi, H. Chen, C.K. Cheng, D. Beckman, and D. Huang, "Layer Count Reduction for Area Array Escape Routing," International Conference and Exhibition on Device Packaging, Scottsdale, Arizona, March 13-16, 2005.
122. B. Yao, L.T. Liu, N.C. Chou, P. Suaris, and C.K. Cheng "Unified Quadratic Programming Approach for Mixed Mode Placement," Int. Symp. on Physical Design, 2005.
123. Y. Hu, H. Chen, Y. Zhu, A.A. Chien, and C.K. Cheng, "Physical Synthesis of Energy-Efficient Networks-on-Chip Through Topology Exploration and Wire Style Optimization," IEEE Inf. Conf. on Computer Design, pp. 111-118 2005.
124. H. Chen, R. Shi, C.K. Cheng, and D.M. Harris, "Surfliner: A Distortionless Electrical Signaling Scheme for Speed of Light On-Chip Communications," IEEE Inf. Conf. on Computer Design, pp. 497-502, 2005.
125. S. Zhou, B. Yao, H. Chen, Y. Zhu, and C.K. Cheng, M. Hutton, "Efficient Static Timing Analysis Using a Unified Framework for False Paths and Multi-Cycle Paths," Asia and South Pacific Design Automation Conf., pp. 73-78, 2006.
126. Z. Zhu, C.K. Cheng, "An Unconditional Stable General Operator Splitting Method for Transistor Level Transient Analysis," Asia and South Pacific Design Automation Conf., pp. 428-433, 2006.
127. Z. Zhou, B. Yao, H. Chen, Y.. Zhu, C.K. Cheng, M. Hutton, T. Collins, S. Srinivasan, N. Chou, P. Suaris, "Improving the Efficiency of Static Timing Analysis with False Paths," IEEE/ACM Int. Conf. on Computer Aided Design, pp. 527-531, 2005.
128. J. Liu, M. Chang, C.K. Cheng, and M. Hutton, "An Iterative Division Algorithm for FPGAs," ACM/SIGDA Int. Symp. on Field-Programmable Gate Arrays, pp. 83-89, 2006.
129. R. Shi, and C.K. Cheng, Efficient Escape Routing for Hexagonal Array of High Density I/Os. ACM/IEEE Design Automation Conf., pp. 1003-1008, 2006.
130. Y. Hu, Y. Zhu, H. Chen, R. Graham, C.K. Cheng, Communication Latency Aware Low Power NoC Synthesis, ACM/IEEE Design Automation Conf., pp. 574-579, 2006.
131. S. Zhou, Y. Hu, R. Graham, C.K. Cheng, and M. Hutton, "Timing Model Reduction for Hierarchical Timing Analysis," IEEE/ACM ICCAD, pp. 415-422, 2006.
132. R. Wang, R. Shi, and C.K. Cheng, "Layer Minimization of Escape Routing in Area Array Packaging,," IEEE/ACM ICCAD, pp. 815-819, 2006.
133. Y. Zhu, T.L. Chen, W. Zhang, T.P. Jung, J.R. Duann, S. Makeig, and C.K. Cheng, Noninvasive Study of the Human Heart using Independent Component Analysis," IEEE Symp. on Bioinformatics and Bioengineering, pp. 340-347, 2006.
134. H. Zhu, R. Shui, H. Chen, C.K. Cheng, A. Deutsch, G. Katopis, "Distortion Minimization for Packaging Level Interconnects," IEEE Electrical Performance of Electronic Packaging, pp. 175-178, 2006.
135. J. Liu, Y. Zhu, H. Zhu, C.K. Cheng, and J. Lillis, "Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space," Asia and South Pacific Design Automation Conf., pp. 609-615, 2007.
136. H. Zhu, Y. Zhu, C.K. Cheng, D. Harris, "An Interconnect-Centric Approach to Cyclic Shifter Design Using Fanout Splitting and Cell Order Optimization," Asia and South Pacific Design Automation Conf., pp. 616-621, 2007.
137. H. Zhu, R. Shi, C.K. Cheng, and H. Chen, "Approaching Speed-of-light Distortionless Communication for On-Chip Interconnect," Asia and South Pacific Design Automation Conf., pp. 684-689, 2007.
138. W. Zhang and C.K. Cheng, "Incremental Power Impedance Optimization Using Vector Fitting Modeling," IEEE Int. Symp. on Circuits and Systems, pp. 2439-2442, 2007.
139. H. Peng and C.K. Cheng, "Fast Transient Simulation of Lossy Transmission Lines," IEEE Int. Symp. on Circuits and Systems, pp. 2706-2709, 2007.
140. L. Zhang, H. Chen, B. Yao, K. Hamilton, C.K. Cheng, "Repeated On-Chip Interconnect Analaysis and Evaluation of Delay, Power, and Bandwidth under Different Design Goals, IEEE Int. Symp. on Quality Electronic Design, pp. 251-256, 2007.
141. Y. Zhu, J. Liu, H. Zhu, C.K. Cheng, "Optimizing Mixed-Radix Ling Adders using Integer Linear Programming," IEEE Int. Workshop on Logic and Synthesis, pp. 75-82, 2007
142. A. Shayan-Arani, Y. Zhu, J.R. Duann, T.P. Jung, S. Makeig, and C.K. Cheng, "Spatial Density Reduction in the Study of the ECG Signal Using Independent Component Analysis," IEEE Int. Conf. of Engineering in Medicine and Biology, pp. 5497, 2007.
143. M. Hashimoto, H. Zhu, C.K. Cheng, "Analytical Eye-diagram Model for On-chip Distortionless Transmission Lines and Its Application to Design Space Exploration," IEEE Custom Integrated Circuits Conf. 2007.
CICC 2007.144. W.P. Zhang, L. Zhang, R. Shi, H. Peng, Z. Zhu, L. Chua-Eoan, R. Murgai, T. Shibuya, N. Ito, C.K. Cheng, "Fast Power Network Analysis with Multiple Clock Domains," IEEE ICCD 2007.
145. C.C. Liu, H. Zhu, and C.K. Cheng, "Passive Compensation For High Performance InterChip Communication," IEEE ICCD 2007.
146. Y. Hu, Y. Zhu, M.B. Taylor, C.K. Cheng, "FPGA Global Routing Architecture Optimization Using a Multicommodity FLow Approach," IEEE ICCD 2007.
147. A. Shayan-Arani, Y. Zhu, Y.N. Cheng, C.K. Cheng, S.F. Lin, P.S. Chen, "Exploring Cardioneural Signal from Noninvasive ECG Measurement," IEEE Symp. on Bioinformatics & Bioengineering 2007.
148. H. Zhu, C.K. Cheng, A. Deutsch, and G. Katopis, "Predicting and Optimizing Jitter and Eye-Opening Based on Bitonic Step Response," IEEE EPEP 2007.
1. C.K. Cheng, Placement Algorithms and Applications to VLSI Design,
Electronics Research Lab. Univ. of California, Berkeley, Memo. UCB/ERL
1984.
2. C.K. Cheng and E.S. Kuh, RAMP: Gate-Array, Standard-Cell and Masterimage
Placement Manual, Electronics Research Lab. Univ. of California, Berkeley,
Memo. UCB/ERL 1984.
3. Y.C. Wei, Ratio Cut Program - The User Manual, Tech. Report Number
CS90-167, CSE Dept., Univ. of California, San Diego, Feb. 1990.
4. C.K. Cheng, CHAMP: Channel Compaction Package Manual, Tech. Report
Number CS92-240, CSE Dept., Univ. of California, San Diego, May 1992.
5. C.W. Yeh, and C.K. Cheng, Ratio Cut Program II, Tech. Report Number
CS92- 250, CSE Dept., Univ. of California, San Diego, July 1992.