Welcome to the CSE 141-Summer 2003 Home page.
Last update: July 29, 2003
Module 9: Finals
(July 30, 2003)
Module 8: Virtual Memory and I/O
(July 28, 2003)
- Virtual Memory
- The need for VM
- Page tables
- Translation lookaside buffers
- Co-existing with caches
- Quiz3 Solutions ( doc,pdf )
- Note the review sessions and TA office hours
- Review discussion session: Tue, Jul 29, 2-4pm, PETER 104
- TA office hours 1-2 (Eric) and 4-5 (Wenjing) on Tue.
- I will be available for questions/office hours Wed 3-5:30 pm in APM3151
Module 7: Memory, Caches and I/O
(July 23, 2003)
- Includes
- Caches
- Locality principles
- Basic SRAM/DRAM organization
- Memory hierarchies
- Direct and set-associative caches
- Performance issues in caches
- Types of cache misses
- Reading: Chapter 7
- Lecture 8 ( ppt,pdf )
- Homework 7 ( doc,pdf )
- Quiz2 Solutions ( doc,pdf )
Module 7: Pipelining
(July 21, 2003)
- Additional Discussion session on (Wed) Jul 23, 2003, Peterson Hall, 12-1pm
- Discussion session on (Tue) Jul 22, 2003, Peterson Hall, 2-4pm
- Includes
- Pipelined datapath
- Data hazards-forwarding and stalls
- Branch hazards
- Interrupts and exceptions
- Superscalar, out-of-order and other cool ideas.
- Reading: Chapter 6.
- Lecture 7 ( ppt,pdf )
- Homework 6 ( doc,pdf )
- Mid-term solutions( doc,pdf )
Module 6: Mid-term and some real stuff CPUs
(July 16, 2003)
- Mid-term!
- Lecture 6 ( pdf )
- Interesting processors we looked at
- ARM, specifically the ARM7TDMI
- The IBM POWER4
- The TI C6x family of DSPs
Module 5: A multi-cycle CPU
(July 14, 2003)
- Includes
- Handling exceptions
- Multi-cycle implementation
- Finite State machines and other ideas for control generation.
- Microcontrollers
- Reading: Chapter 5.4-End.
- Lecture 5 (Udated)( ppt , pdf )
- Homework 5 ( doc , pdf )
- Homework 5 solutions (pdf )
- Quiz1 Solutions ( pdf )
- Interesting links:
- At this point you are ready to look at real world processors such
as the ARM processor. In particular
here
is a presentation describing the basics.
- And here is an old IBM whitepaper on the
PowerPC architecture, which describes the datapath in rather simple terms.
- And here is a bunch of good pictures of the AMD Athlon and Pentium IV datapaths (along with some descriptions). Do not get overwhelmed by the complexity of it all,
but do try to understand what the individual blocks are doing, in particular on the pipelining part.
Module 4: A single cycle CPU: Datapath
(July 9, 2003)
- Includes
- Basic datapath building blocks
- ALU
- Instruction Fetch unit
- Register file
- Instruction and Data memory units
- Three types of MIPS instructions
- Register-Register
- Immediates
- Branches
- Datapath conrresponding to these instructions
- Control management
- Reading: Chapter 5.
- Lecture 4 ( ppt , pdf )
- Homework 4 ( doc , pdf )
- Interesting Links
Module 3: More Arithmetic, Floating Point
(July 7, 2003)
- Stuf we covered
- Basic multiplier design
- The concept behind Booth's multiplier
- Division
- Representation for Floating point
- Floating point Addition, Multiplication and Division
- Reading: Rest of Chapter 4 of the text.
- Lecture 3 ( ppt , pdf )
- Homework 3 : Solve the following textbook problems
- 4.49 and 4.50: a different way of doing adders
- 4.55 and 4.56: problems that show the value of guard and round bits.
- Interesting Links
- A good place to start
for learning more about IEEE Floating Point. Includes some test code for checking
how well your machine does FP.
- The corresponding IEEE site.
- A good place to start
for looking for code that will test your machine for IEEE FP.
- Paranoia
is a FP testing suite (really easy to compile and run) which pushes your machines floating point units edge. Really fun to watch the results.
Interview with
William Kahan which might give you historical context on the IEEE74 floating point
specification. Makes for great reading.
- The GNU Multiple Precision library allows
operations on unlimited bit-length operations.
- Some answers to HW3.
Module 2: Performance, Arithmetic
(July 2, 2003)
- Reading: Chapter 2 and parts of Chapter 4 of the text.
- Lecture 2 ( ppt , pdf )
- Homework 2 ( doc , pdf )
- Some answers to HW2.
- Interesting links
- SPEC is the organization that maintains performance data and the benchmarks
typically run by companies to make "my computer is better than yours" claims.
See SPECBENCH as well as
CPU200 results .
Module 1: Introduction, Instruction Sets
(June 30, 2003)
- Reading: Chapter 1 and Chapter 3 of the text.
-
Lecture 1 (
ppt ,
pdf
)
-
Homework 1 (
doc ,
pdf
)
- Some answers to HW1.
Some interesting links
- SPEC is the organization that maintains performance data and the benchmarks
typically run by companies to make "my computer is better than yours" claims.
See SPECBENCH as well as
CPU200 results .
- A "ridiculously simple ISA" RiSC-16
used in teaching.
Administrivia
Instructor: Tarun
Soni
Teaching Assistants:
Eric Liu,
Wenjing Rao
Time: Monday, Wednesday 6pm-8:50pm
Place: CENTR 119
Section ID: 473213
Office Hours:
Tarun Soni: Monday : 4-6 pm in AP&M 3151
TA Office Hours:
- Eric: Tue, 1-3 pm in APM3337D
- Wenjing: Tue, 3-5pm in APM3337D
Text book: Patterson and Hennessy, Computer
Organization and Design, The Hardware Software Interface, Morgan Kaufman,
Second Edition.
Homeworks: The policy (
html ,
pdf )
Grading: The plan
- Finals, 3hours long, 40%
- Mid-term, about 1.5 hours long, 30%
- Surprise Quizzes, 3 in number, only the top 2 scores will count, about 45 minutes long, 30%
Other stuff: I will try and supplement material in the course with
"hands-on" fun things to do. Examples include running benchmarks on CS machines or testing
CS machines for floating point accuracy. These are not required and certainly not expected
in the course and are primarily meant for your enjoyment, however if you do run some
of these exercises, drop me a note.