We proposed an Event-Driven Simultaneous Compilation model, which exploits on-chip parallelism of multi-core, multithreaded processors. In this framework (called Trident), optimization threads run concurrently with the main executing thread, continuously improving the main thread code. It is called event-driven compilation, because an optimization thread is spawned when the hardware identifies an interesting behavior or pattern, the thread adapts the code to optimize for that behavior, and then exists. We proposed micro-architectural changes and conservative hardware extensions to the existing processor performance monitoring mechanism to trigger optimization events. We also developed a lightweight dynamic compiler to perform classical optimizations as well as aggressive optimizations guided by hardware profiling information. Due to its low overhead of profiling and optimization, Trident can perform recurrent optimization on already optimized code, which is the key to gradually enable more aggressive optimizations or back up from previous bad optimizations.
Trident is powerful to enable parallelization via tradiational as well as non-traditional approaches. We have applied the Trident framework to dynamic value specialization on hot execution traces and to improving performance of memory subsystem (self adaptive inline prefetching via repairing, precomputation thread based prefetching). Other potential applications of Trident include software based profiling and prediction, dynamic code parallelization (via thread level speculation or transactions), and heterogeneous multi-core aware dynamic optimization.
I have extensively modified the Simultaneous Multithreading (SMT) processor simulator to enhance architectural support and evaluate dynamic optimizations.