The Shared-Thread Multiprocessor , Jeffery A. Brown and Dean M. Tullsen, In 22nd ACM International Conference on Supercomputing, June, 2008.
Accurate Branch Prediction for Short Threads, BumYong Choi, Leo Porter, Dean M. Tullsen, In Thirteenth International Conference on Architectural Support for Programming Languages and Operating Systems, April, 2008.
Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture, Subhradyuti Sarkar and Dean M. Tullsen, In 2008 International Conference on High Performance Embedded Architectures & Compilers, January, 2008. Also, LNCS vol. 4917.
"The Architecture of Efficient Multi-Core Processors: A Holistic Approach", Rakesh Kumar and Dean M. Tullsen, In Advances in Computers, Volume 69 (M. Zelkowitz, Ed.), Academic Press, 2007, pp. 1-87.
Proximity-Aware Directory-Based Coherence for Multi-core Processor Architectures, Jeffery A. Brown, Rakesh Kumar, and Dean M. Tullsen, In 19th ACM Symposium on Parallelism in Algorithms and Architectures, June, 2007.
Accelerating and Adapting Precomputation Threads for Efficient Prefetching, Weifeng Zhang, Dean M. Tullsen, Brad Calder, In 13th International Symposium on High Performance Computer Architecture, January, 2007.
Dynamic Code Value Specialization Using the Trace Cache Fill Unit, Weifeng Zhang, Steve Checkoway, Brad Calder, and Dean M. Tullsen, In 24th International Conference on Computer Design, October, 2006.
Application-Specific Customization of Parameterized FPGA Soft-Core Processors, David Sheldon, Rakesh Kumar, Roman Lysecky, Frank Vahid, and Dean M. Tullsen, In 2006 International Conference on Computer-Aided Design, November, 2006.
Conjoining Soft-Core FPGA Processors, David Sheldon, Rakesh Kumar, Frank Vahid, Dean M. Tullsen, and Roman Lysecky, In 2006 International Conference on Computer-Aided Design, November, 2006.
Core Architecture Optimization for Heterogeneous Chip Multiprocessors, Rakesh Kumar, Dean M. Tullsen, and Norman P. Jouppi, In 15th International Symposium on Parallel Architecture and Compilation Techniques, September, 2006.
Exploiting Unbalanced Thread Scheduling for Energy and Performance on a CMP of SMT Processors, Matthew DeVuyst, Rakesh Kumar, and Dean M. Tullsen, In 2006 IEEE International Parallel and Distributed Processing Symposium, April, 2006.
A Self-Repairing Prefetcher in an Event-Driven Dynamic Optimization Framework, Weifeng Zhang, Brad Calder, and Dean M. Tullsen, In 4th International Symposium on Code Generation and Optimization (CGO), March, 2006.
Heterogeneous Chip Multiprocessing, Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi, and Parthasarathy Ranganathan, IEEE Computer, November 2005, pp. 32-38.
An Event-Driven Multithreaded Dynamic Optimization Framework, Weifeng Zhang, Brad Calder, and Dean M. Tullsen, In 2005 International Conference on Parallel Archtectures and Compilation Techniques, September, 2005.
Mitosis Compiler: An Infrastructure for Speculative Threading Based on Pre-Computation Slices, Carlos García Quiñones, Carlos Madriles, Jesús Sánchez, Pedro Marcuello, Antonio González and Dean M. Tullsen, In 2005 Conference on Programning Language Design and Implementation, June, 2005.
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling, Rakesh Kumar, Victor Zyuban, Dean M. Tullsen, In 32nd International Symposium on Computer Architecture, June, 2005.
A Tree Based Router Search Engine Architecture With Single Port Memories, Florin Baboescu, Dean M. Tullsen, Grigore Rosu, Sumeet Singh, In 32nd International Symposium on Computer Architecture, June, 2005.
Multithreaded Value Prediction, Nathan Tuck, Dean M. Tullsen, In 11th International Symposium on High Performance Computer Architecture, February, 2005.
Architecture-Level Power Optimizations -- What Are the Limits?, John S. Seng, Dean M. Tullsen, Journal of Instruction Level Parallelism, 7 (2005), January, 2005.
The Danger of Interval-Based Power Efficiency Metrics: When Worst Is Best, Yiannakis Sazeides, Rakesh Kumar, Dean M. Tullsen, Theofanis Constantinou, In Computer Architecture Letters, Volume 4, January, 2005.
Control Flow Optimizations Via Dynamic Reconvergence Prediction, Jamison D. Collins, Dean M. Tullsen, Hong Wang, In 37th International Symposium on Microarchitecture, December, 2004.
Balanced Multithreading: Increasing Throughput Via a Low Cost Multithreading Hierarchy, Eric Tune, Rakesh Kumar, Dean M. Tullsen, Brad Calder, In 37th International Symposium on Microarchitecture, December, 2004.
Conjoined-Core Chip Multiprocessing, Rakesh Kumar, Norman P. Jouppi, Dean M. Tullsen, In 37th International Symposium on Microarchitecture, December, 2004.
Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance, Rakesh Kumar, Dean M. Tullsen, Partha Ranganathan, Norman P. Jouppi, Keith I. Farkas, In 31st International Symposium on Computer Architecture, June, 2004.
Clustered Multithreaded Architectures -- Pursuing Both IPC and Cycle Time, Jamison D. Collins, Dean M. Tullsen, In 18th International Parallel and Distributed Processing Symposium, April, 2004.
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction, Rakesh Kumar, Keith Farkas, Norm P. Jouppi, Partha Ranganathan, Dean M. Tullsen, In 36th International Symposium on Microarchitecture, December, 2003.
Exploring the Potential of Architecture-Level Power Optimizations, John S. Seng, Dean M. Tullsen, In Third International Workshop on Power-Aware Computer Systems, December, 2003. Also published in Lecture Notes in Computer Science, Volume 3164, December, 2004.
Initial Observations of a Simultaneous Multithreading Processor, Nathan Tuck, Dean M. Tullsen, In Twelfth International Conference on Parallel Architectures and Compilation Techniques, September, 2003.
A Multi-Core Approach to Addressing the Energy-Complexity Problem in Microprocessors, Rakesh Kumar, Keith Farkas, Norm P. Jouppi, Partha Ranganathan, Dean M. Tullsen, In 2003 Workshop on Complexity-Effective Design, June, 2003.
Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures, Rakesh Kumar, Keith Farkas, Norm P. Jouppi, Partha Ranganathan, Dean M. Tullsen, Computer Architecture Letters, Volume 2, Apr. 2003
The Effect of Compiler Optimizations on Pentium 4 Power Consumption, John S. Seng, Dean M. Tullsen, In the 7th Annual Workshop on Interaction between Compilers and Computer Architectures, February, 2003
Pointer-Cache Assisted Prefetching, Jamison Collins, Suleyman Sair, Brad Calder, and Dean Tullsen, In 35th Annual International Symposium on Microarchitecture, November 2002.
Compiling for Instruction Cache Performance on a Multithreaded Architecture, Rakesh Kumar, Dean M. Tullsen, In 35th Annual International Symposium on Microarchitecture, November 2002.
Quantifying Instruction Criticality, Eric Tune, Dean Tullsen, and Brad Calder, In Eleventh International Conference on Parallel Architectures and Compilation Techniques, September 2002.
Symbiotic Jobscheduling with Priorities for a Simultaneous Multithreading Processor, Allan Snavely, Dean M. Tullsen, Geoff Voelker, In 2001 International Conference on Measurement and Modeling of Computer Systems (Sigmetrics 02), June, 2002 (see abstract).
Dynamic Speculative Precomputation, Jamison D. Collins, Dean M. Tullsen, Hong Wang, John P. Shen, In 34th Annual International Symposium on Microarchitecture, December, 2001 (see abstract).
Reducing Power with Dynamic Critical Path Information, John S. Seng, Eric S. Tune, Dean M. Tullsen, In 34th Annual International Symposium on Microarchitecture, December, 2001 (see abstract).
Handling Long-Latency Loads in a Simultaneous Multithreading Processor, Dean M. Tullsen, Jeff A. Brown, In 34th Annual International Symposium on Microarchitecture, December, 2001 (see abstract).
Speculative Precomputation: Long-range Prefetching of Delinquent Loads, Jamison D. Collins, Hong Wang, Dean M. Tullsen, Christopher Hughes, Yong-Fong Lee, Dan Lavery, John P. Shen, In 28th International Symposium on Computer Architecture, July, 2001 (see abstract).
Dynamic Prediction of Critical Path Instructions, Eric Tune, Dongning Liang, Dean M. Tullsen, Brad Calder, In 7th International Symposium on High Performance Computer Architecture, January, 2001 (see abstract).
Symbiotic Jobscheduling for a Simultaneous Multithreading Processor, Allan Snavely, Dean M. Tullsen, In Ninth International Conference on Architectural Support for Programming Languages and Operating Systems, November, 2000 (see abstract).
Power-Sensitive Multithreaded Architecture, John S. Seng, Dean M. Tullsen, George Z.N. Cai, In International Conference on Computer Design 2000, September, 2000 (see abstract).
Limits of Task-based Parallelism in Irregular Applications, Barbara Kreaseck, Dean M. Tullsen, Brad Calder, In Third International Symposium on High Performance Computing, October, 2000 (see abstract). (a version of this paper also appeared in Interact-4). Best Student Paper award.
Hardware Identification of Cache Conflict Misses, Jamison D. Collins, Dean M. Tullsen, In 32nd Annual International Symposium on Microarchitecture, November, 1999 (see abstract).
ILP versus TLP on SMT, Nick Mitchell, Larry Carter, Jeanne Ferrante, and Dean Tullsen, Supercomputing '99, November 1999.
Classifying Load and Store Instructions for Memory Renaming, Glenn Reinman, Brad Calder, Dean Tullsen, Gary Tyson, and Todd Austin, In ACM International Conference on Supercomputing, June 1999.
Storageless Value Prediction Using Prior Register Values, Dean M. Tullsen, John S. Seng, In 26th International Symposium on Computer Architecture, May, 1999 (see abstract).
Selective Value Prediction, Brad Calder, Glenn Reinman, and Dean M. Tullsen, In 26th International Symposium on Computer Architecture, May, 1999 (see abstract).
Software-Directed Register Deallocation for Simultaneous Multithreaded Processors, Jack L. Lo, Sujay S. Parekh, Susan J. Eggers, Henry M. Levy, and Dean M. Tullsen, IEEE Transactions on Parallel and Distributed Systems, to appear (see abstract).
Instruction Recycling on a Multiple-Path Processor, Steven Wallace, Dean M. Tullsen, Brad Calder, In 5th International Symposium on High Performance Computer Architecture, January, 1999 (see abstract).
Supporting Fine-Grained Synchronization on a Simultaneous Multithreading Processor, Dean M. Tullsen, Jack L. Lo, Susan J. Eggers, Henry M. Levy, In 5th International Symposium on High Performance Computer Architecture, January, 1999 (see abstract, amplified technical report, published version).
Explorations in Symbiosis on Two Multithreaded Architectures, Allan Snavely, Nick Mitchell, Larry Carter, Jeanne Ferrante, Dean Tullsen, In Workshop on Multithreaded Execution, Architecture, and Compilation, January, 1999.
Threaded Multiple Path Execution, Steven Wallace, Brad Calder, Dean M. Tullsen, In 25th Annual International Symposium on Computer Architecture, June, 1998 (see abstract).
Tuning Compiler Optimizations for Simultaneous Multithreading, Jack L. Lo, Susan J. Eggers, Henry M. Levy, Sujay S. Parekh, Dean M. Tullsen, In 30th Annual International Symposium on Microarchitecture (Micro-30), Dec. 1-3, 1997 (see abstract).
Simultaneous Multithreading: A Foundation for Next-generation Processors, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, Rebecca L. Stamm, and Dean M. Tullsen, IEEE Micro, September/October 1997, pp. 12-18.
Converting Thread-Level Parallelism Into Instruction-Level Parallelism via Simultaneous Multithreading Jack L. Lo, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Rebecca L. Stamm, and Dean M. Tullsen, ACM Transactions on Computer Systems, August 1997, pp. 322-354. (see abstract)
Simultaneous Multithreading, D.M. Tullsen, Ph.D. Thesis, University of Washington, August, 1996.
Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor, D.M. Tullsen, S.J. Eggers, J.S. Emer, H.M. Levy, J.L. Lo, and R.L. Stamm,In 23rd Annual International Symposium on Computer Architecture, May, 1996 (see abstract). REPRINTED IN Readings in Computer Architecture.
Simultaneous Multithreading: Maximizing On-Chip Parallelism, D.M. Tullsen, S.J. Eggers, and H.M. Levy,In 22nd Annual International Symposium on Computer Architecture, June, 1995 (see abstract). REPRINTED IN 25 Years of the International Symposia on Computer Architecture: Selected Papers, 1998.
Simulation and Modeling of a Simultaneous Multithreading Processor, D.M. Tullsen,In the 22nd Annual Computer Measurement Group Conference, December, 1996
Effective Cache Prefetching on Bus-Based Multiprocessors, D.M. Tullsen, S.J. Eggers, ACM Transactions on Computer Systems, pp. 57-88, February, 1995 (see abstract)
Limitations of Cache Prefetching on a Bus-Based Multiprocessor, D.M. Tullsen, S.J. Eggers, In 20th Annual International Symposium on Computer Architecture, pp 278-288, May, 1993 (see abstract)
Design and VLSI Implementation of an Online Algorithm, D.M. Tullsen, M.D. Ercegovac, Real Time Signal Processing IX, August, 1988
If you have comments or suggestions, email me at tullsen at cs.ucsd.edu